CSL3.x INTC - support for nested interrupts and reading Timer count from running Timer in ISR context?

Team,

I am looking at the C66x CSL INTC and Timer module from at the pdk_c6678_1_1_2_6\packages\ti\csl\example\timer_test.c example.
It is slightly modified to read the COUNT in the Timer ISR while timer is still running. But the Timer CNT is always read as 0 (unless a break point is placed on it).
Could you please confirm my understanding about the INTC and timer below?

Looking at the code:

static Int32 test_high_single_shot_timer (Uint8 IntcInstance)
{
    ....     
    /* Open INTC */
    vectId = CSL_INTC_VECTID_13;
    tmrIntcHandle = CSL_intcOpen(&tmrIntcObj, CSL_GEM_TINTHN, &vectId, NULL);
	...   
    /* Bind ISR to Interrupt */
    EventRecord.handler = (CSL_IntcEventHandler)&TimerInterruptHandler;
    EventRecord.arg     = (void *)CSL_GEM_TINTLN;
    CSL_intcPlugEventHandler(tmrIntcHandle, &EventRecord);
	...
}

static void TimerInterruptHandler (void *arg)
{
    /* Increment the number of interrupts detected. */
    timerISRCounter++;
	
	// !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
    // the following code always reads TMR COUNT_LO as 0. Why?
    CSL_tmrGetHwStatus(hTmr, CSL_TMR_QUERY_COUNT_LO, (Uint32*)(&myCount));    
    // !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!

    /* Clear the event ID. */
    CSL_intcEventClear((CSL_IntcEventId)arg);
}

a) The interrupt C keyword does not need to be used in the TimerInterruptHandler ISR as the _CSL_intcDispatcher fct is anyway called first (which is transparent to the user). _CSL_intcDispatcher declaration contains the interrupt keyword.
Correct?

b) Looking at C66x instruction set - SPRUGH7 section 6.2 and 6.6.2 it seems that the CPU interrupts are disabled (automatically by HW) during interrupt processing and get re-enabled when returning from the ISR (CPU copies back PGIE to GIE).

I have not seen any code in the CSL INTC (specifically in _CSL_intcDispatcher) that does re-enable the interrupts. So it seems that the CSL INTC does not support nested interrupts. Using the CSL INTC a maskable interrupt will not interrupt an other maskable interrupt. The running ISR must exit before next maskable interrupt can be taken.
So when using the CSL there is no need to add to the ISR any code to disable and re-enable the interrupts to protected it against potential other maskable interrupts.
Correct?

c) Reading COUNT register of a running timer in the Timer ISR:
The problem with the ISR above is that the value read from CNTLO register is always 0. The only way to read a correct value is to place a break point at this line of code.

There do not seem to be any restriction to read register of a running counter. Some restriction are given in section 3.9 "Timer operation Boundary condition" - SPRUGV5a but nothing specifically about reading restrictions.

From a) and b) I don't see neither restriction from doing this from a CSL interrupt context.

What could be the reasons why the CNTLO is always read as 0?


Thanks in advance,
Anthony

#1-1821105550