• State TI Thinks Resolved
  • Locked Locked
  • Replies 2 replies
  • Answers 1 answer
  • Subscribers 99 subscribers
  • Views 260 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

EDMACC0 IPRH problem

Milan Yagodich
Prodigy 220 points

I have a generic routine that processes interrupts from the 3 edma controllers: CC0, CC1 and CC2.  I have no problems with CC1 and CC2, but on CC0, when I read the interrupt high pending register IPRH, I get bogus values.  I've stepped through the assembly code and it is correct. 

Looking in memory at 0x02701062 , it shows 0 for the contents of IPRH.  The register view also shows IPRH as  0.  But when I read the memory directly through the CSL function, it returns a non-zero number.


I realize that there are only 16 events for CC0, but I thought that any TCC number (0-63) could be put into the param block and that bit would be set in IPR/IPRH.

Is there something that I am not configuring correctly, or is this a silicon bug?


This is a C6670 multicore dsp.

Thanks

Milan

  • 0
    TI__Mastermind 22391 points

    Milan

    i will send you a separate email on the answer and how to debug this..

    Mohsen

  • 0
    TI__Mastermind 35645 points

    Hi,

    Thanks for your post.

    To my understanding, we could trigger up to 64 DMA channels through 64 peripheral/master DMA Tx/Rx events which constitutes all channel controllers. What is your TCC value captured in OPT?

    May be, i could recommend few suggestion below:

    1. Ensure whether TCINTEN bit is enabled in channel OPT and only then, the interrupt pending register (IPR / IPRH) relevant bit position appropriate to the DMA event would be set on transfer completion

    2. Also, please ensure the TCCMODE bit in OPT which would indicate normal or early completion of data transfer. To clarify you that any TCC value cannot be set in the PaRAM and the fact is that the 6-bit TCC would be posted by the TC to the CC after it receives the transfer completion signal from the destination peripheral in normal completion mode. This 6-bit code sets the relevant bit in the interrupt pending register (IPR [TCC] / IPRH [TCC]) for interrupt triggered.

    3. I would suggest you to validate the received TCC code in OPT first and obviously, the corresponding bit position in IPR/IPRH would be set which is directly the TCC value and thereafter, the corresponding IER[TCC] / IERH [TCC] bit would be set to generate a EDMA completion interrupt to the DSP

    Thanks & regards,

    Sivaraj K

    -------------------------------------------------------------------------------------------------------

    Please click the Verify Answer button on this post if it answers your question.

    -------------------------------------------------------------------------------------------------------