bus priority between CPU and EDMA on C6657.

Hi,

Thanks for your post.

In general, corepacs bus priorities are set through software in the UMC control registers and all the packet-DMA-based peripherals also have internal registers to define the priority level of their initiated transactions. Some masters do not have priority allocation register of their own. For these masters, a priority allocation register (PKTDMA_PRI) is provided for them. Please refer section 5.4 from the c6657 datasheet below:

http://www.ti.com/lit/ds/sprs814b/sprs814b.pdf

Also, please check the CFG arbitration control register (ECFGARBE) which controls the priority for the configuration bus transactions from extended memory controller (EMC). Kindly refer section 8.3.6 from c66x corepac user guide as below:

http://www.ti.com/lit/ug/sprugw0c/sprugw0c.pdf

Thanks & regards,

Sivaraj K

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