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Query on PWM frequency configuration on AM335x

Veena kudva
Prodigy 160 points

Hi 

I am configuring the PWM on AMX3359  for the following setting .

case 1 :

/* Configuration of PWM TBCLK to 1.25 MHz*/

#define CLOCK_DIV_VAL (80)
#define SOC_EHRPWM_1_MODULE_FREQ (100000000)

I have configured the period register " EHRPWM_TBPRD" to hold a value of 255.

As per calculations  the PWM period generated should be 204 us . When I measure the period using a CRO I get 144 us.

Am i missing any other configuration setting ?

When I tried for the setting below :

Case 2: 

/* Configuration of PWM TBCLK to 25 MHz*/

#define CLOCK_DIV_VAL (4)
#define SOC_EHRPWM_1_MODULE_FREQ (100000000)

I get the correct PWM period of 10.2 us.

Why I am getting wrong values for TBCLK at lower frequencies as in Case 1 ?

Thanks.

Regards,

Veena

 

  • 0
    TI__Guru**** 393215 points

    Hi Veena,

    Please post the contents of the TBCTL register in both cases.

  • 0 in reply to Biser Gatchev-XID
    Prodigy 160 points
    Hi Biser ,

    I am using the Staterware API's .


    Case 1 : Configuration of PWM TBCLK to 1.25 MHz

    #define CLOCK_DIV_VAL (80)
    #define SOC_EHRPWM_1_MODULE_FREQ (100000000)

    /* TimeBase configuration */
    /* Configure the clock frequency */
    EHRPWMTimebaseClkConfig(SOC_EPWM_1_REGS,
    SOC_EHRPWM_1_MODULE_FREQ/CLOCK_DIV_VAL,
    SOC_EHRPWM_1_MODULE_FREQ);


    /* Configure the period of the output waveform */
    EHRPWMPWMOpFreqSet(SOC_EPWM_1_REGS,
    SOC_EHRPWM_1_MODULE_FREQ/CLOCK_DIV_VAL,
    (unsigned int)(SOC_EHRPWM_1_MODULE_FREQ/CLOCK_DIV_VAL/255),
    (unsigned int)EHRPWM_COUNT_UP,
    (bool)EHRPWM_SHADOW_WRITE_DISABLE);



    Case 2 : Configuration of PWM TBCLK to 25 MHz

    #define CLOCK_DIV_VAL (4)
    #define SOC_EHRPWM_1_MODULE_FREQ (100000000)

    /* TimeBase configuration */
    /* Configure the clock frequency */
    EHRPWMTimebaseClkConfig(SOC_EPWM_1_REGS,
    SOC_EHRPWM_1_MODULE_FREQ/CLOCK_DIV_VAL,
    SOC_EHRPWM_1_MODULE_FREQ);


    /* Configure the period of the output waveform */
    EHRPWMPWMOpFreqSet(SOC_EPWM_1_REGS,
    SOC_EHRPWM_1_MODULE_FREQ/CLOCK_DIV_VAL,
    (unsigned int)(SOC_EHRPWM_1_MODULE_FREQ/CLOCK_DIV_VAL/255),
    (unsigned int)EHRPWM_COUNT_UP,
    (bool)EHRPWM_SHADOW_WRITE_DISABLE);


    Regards,
    Veena
  • 0 in reply to Veena kudva
    TI__Guru**** 393215 points

    Sorry, we don't support Starterware on this forum. There is a dedicated forum for it: https://e2e.ti.com/support/embedded/starterware/f/790 However please check section 15.2.4.1 from the AM335X TRM Rev. L You will see that:

    TBCLK = SYSCLKOUT/(HSPCLKDIV * CLKDIV)

    Check whether you don't have HSPCLKDIV set somewhere.

  • 0 in reply to Biser Gatchev-XID
    Prodigy 160 points
    Hi Biser,

    I checked the TBCTL values.


    Case 1 : Configuration of PWM TBCLK to 1.25 MHz

    TBCTL = 0x 0BB8 ( 0000 0010 0010 1000)

    Bit (9-7) ---> HSPCLKDIV
    Bit(10 -12) ----> CLKDIV

    So HSPCLKDIV = 111 = 7 ( 1/14)
    CLKDIV = 010 = 2 =( 1/4)

    TBCLK = SYSCLKOUT/(HSPCLKDIV * CLKDIV)

    TBCLK = 100/(14*4) = 1.78 M hz ( Should have been 1.25 MHZ)


    Case 1 : Configuration of PWM TBCLK to 25 MHz

    TBCTL = 0x 0138 = 0000 0001 0011 1000

    So HSPCLKDIV = 010 = 2 ( 1/4)
    CLKDIV = 000 = 0 =( 1)

    TBCLK = 100/4) = 25M hz ( Correct)



    Regards,
    Veena
  • 0 in reply to Veena kudva
    TI__Guru**** 393215 points

    I supposed it's something like that. You simply need to find the correct values of HSPCLKDIV and CLKDIV to get the desired frequency.