GPMC Clock in Beagle bone black

jithendra kumar

Other Parts Discussed in Thread: SYSCONFIG

Hi,

I am Jithendra, I am trying to configure gpmc on Beagle bone black to send data to FPGA. For this, we made a .dts file and compiled successfully.

My requirement is to configure the GPMC in Synchronous 8 bit NOR device Mode. So as per Sitara RFM, we configured the configs like this

Config 1: 0x29000003;

Config 2 : 0x00020200;

Config 3 : 0x22010110;

Config 4 : 0x02016211;

Config 5 : 0x01010202;

Config 6 : 0x80000000;

Config 7 : 0x00000f41;

Also, we enabled the 1) GPMC_TIMEOUT_CONTROL by setting it as 0x00001ff1.

2) CM_PER_GPMC_CLKCTRL by setting it as 0x00000002.

But, problem is that we are not getting the GPMC clock when we checked the P8-21 Pin by connecting to the CRO.

Do we need to set any other clock registers to enable the GPMC?

Can any one help us on how to configure the Gpmc so that, we should be able to capture the GPMC clock on CRO.

over 10 years ago

0 Biser Gatchev-XID over 10 years ago

TI__Guru**** 393215 points

Hi,

GPMC clock is output in synchronous mode only. This is not a free running clock. It's output only during GPMC transactions.

0 jithendra kumar over 10 years ago in reply to Biser Gatchev-XID

Prodigy 180 points

Hi Biser,

Thanks for your reply.
We infact checked for the GPMC clock in uboot by writing some values at cs0 base address using "mw 0x01000000 0x12345678"
Even then, we were not able to see the clock cycles on Pin 21 on P8 header.

Regards,
Jithendra

0 Biser Gatchev-XID over 10 years ago in reply to jithendra kumar

TI__Guru**** 393215 points

Have you configured pinmux for the GPMC pins you require?

0 jithendra kumar over 10 years ago in reply to Biser Gatchev-XID

Prodigy 180 points

We configured the P8 and P9 header pins using dts file:
/dts-v1/;
/plugin/;

/ {
compatible = "ti,beaglebone", "ti,beaglebone-black";

/* identification */
part-number = "BB-BONE-GPMC";
version = "00A0";

/* state the resources this cape uses */
exclusive-use =
/* the pin header uses */
"P8.25", /* gpmc: gpmc_ad0 */
"P8.24", /* gpmc: gpmc_ad1 */
"P8.5", /* gpmc: gpmc_ad2 */
"P8.6", /* gpmc: gpmc_ad3 */
"P8.23", /* gpmc: gpmc_ad4 */
"P8.22", /* gpmc: gpmc_ad5 */
"P8.3", /* gpmc: gpmc_ad6 */
"P8.4", /* gpmc: gpmc_ad7 */
"P8.19", /* gpmc: gpmc_ad8 */
"P8.13", /* gpmc: gpmc_ad9 */
"P8.14", /* gpmc: gpmc_ad10 */
"P8.17", /* gpmc: gpmc_ad11 */
"P8.12", /* gpmc: gpmc_ad12 */
"P8.11", /* gpmc: gpmc_ad13 */
"P8.16", /* gpmc: gpmc_ad14 */
"P8.15", /* gpmc: gpmc_ad15 */
"P9.13", /* gpmc: gpmc_wpn */
"P8.21", /* gpmc: gpmc_csn1 */
"P8.18", /* gpmc: gpmc_wait1*/
"P8.7", /* gpmc: gpmc_advn_ale */
"P8.8", /* gpmc: gpmc_oen_ren */
"P8.10", /* gpmc: gpmc_wen */
"P8.9", /* gpmc: gpmc_ben0_cle */
"P8.45", /* gpmc: gpmc_a0 */
"P8.46", /* gpmc: gpmc_a1 */
"P8.43", /* gpmc: gpmc_a2 */
"P8.44", /* gpmc: gpmc_a3 */
"P8.41", /* gpmc: gpmc_a4 */
"P8.42", /* gpmc: gpmc_a5 */
"P8.39", /* gpmc: gpmc_a6 */
"P8.40", /* gpmc: gpmc_a7 */
"P8.27", /* gpmc: gpmc_a8 */
"P8.29", /* gpmc: gpmc_a9 */
"P8.28", /* gpmc: gpmc_a10 */
"P8.30", /* gpmc: gpmc_a11 */
"P8.37", /* gpmc: gpmc_a12 */
"P8.38", /* gpmc: gpmc_a13 */
"P8.36", /* gpmc: gpmc_a14 */
"P8.34", /* gpmc: gpmc_a15 */
"P8.35", /* gpmc: gpmc_a16 */
"P8.33", /* gpmc: gpmc_a17 */
"P8.31", /* gpmc: gpmc_a18 */
"P8.32", /* gpmc: gpmc_a19 */
"P8.20", /* gpmc: gpmc_csn2 */
"P8.21", /* gpmc: gpmc_clk */
"P9.11", /* gpmc: gpmc_wait0 */
"P8.26", /* gpmc: gpmc_csn0 */
"gpmc", /* the reset pin */
"eMMC_RSTn";

#address-cells = <1>;
#size-cells = <1>;

fragment@0 {
target = <&am33xx_pinmux>;
__overlay__ {

gpmc_pins: pinmux_gpmc_pins {
pinctrl-single,pins = <
0x000 0x30 /* gpmc_ad0.gpmc_ad0 MODE0 | INPUT | PULLUP */
0x004 0x30 /* gpmc_ad1.gpmc_ad1 MODE0 | INPUT | PULLUP */
0x008 0x30 /* gpmc_ad2.gpmc_ad2 MODE0 | INPUT | PULLUP */
0x00C 0x30 /* gpmc_ad3.gpmc_ad3 MODE0 | INPUT | PULLUP */
0x010 0x30 /* gpmc_ad4.gpmc_ad4 MODE0 | INPUT | PULLUP */
0x014 0x30 /* gpmc_ad5.gpmc_ad5 MODE0 | INPUT | PULLUP */
0x018 0x30 /* gpmc_ad6.gpmc_ad6 MODE0 | INPUT | PULLUP */
0x01C 0x30 /* gpmc_ad7.gpmc_ad7 MODE0 | INPUT | PULLUP */
0x020 0x30 /* gpmc_ad8.gpmc_ad8 MODE0 | INPUT | PULLUP */
0x024 0x30 /* gpmc_ad9.gpmc_ad9 MODE0 | INPUT | PULLUP */
0x028 0x30 /* gpmc_ad10.gpmc_ad10 MODE0 | INPUT | PULLUP */
0x02C 0x30 /* gpmc_ad11.gpmc_ad11 MODE0 | INPUT | PULLUP */
0x030 0x30 /* gpmc_ad12.gpmc_ad12 MODE0 | INPUT | PULLUP */
0x034 0x30 /* gpmc_ad13.gpmc_ad13 MODE0 | INPUT | PULLUP */
0x038 0x30 /* gpmc_ad14.gpmc_ad14 MODE0 | INPUT | PULLUP */
0x03C 0x30 /* gpmc_ad15.gpmc_ad15 MODE0 | INPUT | PULLUP */
0x074 0x08 /* gpmc_wpn.gpmc_wpn MODE0 | OUTPUT */
0x08C 0x28 /*gpmc_cscn1.gpmc_cscn11 MODE0 | OUTPUT */
0x090 0x2A /* gpmc_wait1.gpmc_wait1 MODE2 | input */
0x094 0x08 /* gpmc_advn_ale.gpmc_advn_ale MODE0 | OUTPUT */
0x098 0x08 /* gpmc_oen_ren.gpmc_oen_ren MODE0 | OUTPUT */
0x09c 0x08 /* gpmc_wen.gpmc_wen MODE0 | OUTPUT */
0x078 0x08 /* gpmc_ben0_cle.gpmc_ben0_cle MODE0 | OUTPUT */
0x0E0 0x01 /* gpmc_a8.gpmc_a8 MODE1 | INPUT | PULLUP */
0x0E8 0x01 /* gpmc_a10.gpmc_a10 MODE1 | INPUT | PULLUP */
0x0E4 0x01 /* gpmc_a9.gpmc_a9 MODE1 | INPUT | PULLUP */
0x0EC 0x01 /* gpmc_a11.gpmc_a11 MODE1 | INPUT | PULLUP */
0x0D8 0x01 /* gpmc_a18.gpmc_a18 MODE1 | INPUT | PULLUP */
0x0DC 0x01 /* gpmc_a19.gpmc_a19 MODE1 | INPUT | PULLUP */
0x0D4 0x01 /* gpmc_a17.gpmc_a17 MODE1 | INPUT | PULLUP */
0x0CC 0x01 /* gpmc_a15.gpmc_a15 MODE1 | INPUT | PULLUP */
0x0D0 0x01 /* gpmc_a16.gpmc_a16 MODE1 | INPUT | PULLUP */
0x0C8 0x01 /* gpmc_a14.gpmc_a14 MODE1 | INPUT | PULLUP */
0x0C0 0x01 /* gpmc_a12.gpmc_a12 MODE1 | INPUT | PULLUP */
0x0C4 0x01 /* gpmc_a13.gpmc_a13 MODE1 | INPUT | PULLUP */
0x0B8 0x01 /* gpmc_a6.gpmc_a6 MODE1 | INPUT | PULLUP */
0x0BC 0x01 /* gpmc_a7.gpmc_a7 MODE1 | INPUT | PULLUP */
0x0B0 0x01 /* gpmc_a4.gpmc_a4 MODE1 | INPUT | PULLUP */
0x0B4 0x01 /* gpmc_a5.gpmc_a5 MODE1 | INPUT | PULLUP */
0x0A8 0x01 /* gpmc_a2.gpmc_a2 MODE1 | INPUT | PULLUP */
0x0AC 0x01 /* gpmc_a3.gpmc_a3 MODE1 | INPUT | PULLUP */
0x0A0 0x01 /* gpmc_a0.gpmc_a0 MODE1 | INPUT | PULLUP */
0x0A4 0x01 /* gpmc_a1.gpmc_a1 MODE1 | INPUT | PULLUP */
0x084 0x08 /* gpmc_be1n.gpmc_be1n MODE 0 | OUTPUT | PULLDOWN */
0X080 0X09 /* gpmc_clk.gpmc_clk MODE 1 | OUTPUT */
0x070 0x30 /* gpmc_wait0.gpmc_wait0 MODE 0 | INPUT | PULLUP */
0x07C 0x08 /* gpmc_csn0.gpmc_csn0 MODE 0 | OUTPUT | PULLDOWN */
>;
};

};
};

fragment@1 {
target = <&gpmc>;
depth = <1>; /* only create devices on depth 1 */

/* stupid warnings */
#address-cells = <1>;
#size-cells = <1>;

__overlay__ {

status = "okay";

#address-cells = <2>;
#size-cells = <1>;

pinctrl-names = "default";
pinctrl-0 = <&gpmc_pins>;

};

};

};

0 Biser Gatchev-XID over 10 years ago in reply to jithendra kumar

TI__Guru**** 393215 points

This seems OK, though you should check that it doesn't get overwritten by MMC1 pinmux settings.

The major problem that you have is that you have selected GPMC_CLK = GPMC_CLK / 4, but perhaps you haven't noticed that all timings are given in GPMC_FCLK cycles. For a simple check simply set bits [1:0] in GPMC_CONFIG1 to 00b.

In pinmux change:

0x080 0x09 /* gpmc_clk.gpmc_clk MODE 1 | OUTPUT */

to:

0x080 0x29 /* gpmc_clk.gpmc_clk MODE 1 | INPUT */

otherwise your read accesses will not work.

0 jithendra kumar over 10 years ago in reply to Biser Gatchev-XID

Prodigy 180 points

Hi Biser,

Even We changed the Config 1 [0:1] bits, but clock is not coming out. Is there required any other config to see the clock.

Here I set config like this

mw 0x44e00030 0x02; // gpmc clock enabling
mw 0x50000040 0x1ff1;

//these settings are for making GPIO to GPMC

mw 0x44e10800 0x30;
mw 0x44e10804 0x30;
mw 0x44e10808 0x30;
mw 0x44e1080c 0x30;
mw 0x44e10810 0x30;
mw 0x44e10814 0x30;
mw 0x44e10818 0x30;
mw 0x44e1081c 0x30;
mw 0x44e10820 0x30;

mw 0x44e10824 0x30;
mw 0x44e1082c 0x30;
mw 0x44e10830 0x30;
mw 0x44e10834 0x30;
mw 0x44e10838 0x30;
mw 0x44e1083c 0x30;
mw 0x44e10840 0x01;
mw 0x44e10844 0x01;
mw 0x44e10848 0x01;
mw 0x44e1084c 0x01;

mw 0x44e10850 0x01;
mw 0x44e10854 0x01;
mw 0x44e10858 0x01;
mw 0x44e1085c 0x01;
mw 0x44e10860 0x01;
mw 0x44e10864 0x01;
mw 0x44e10868 0x01;
mw 0x44e1086c 0x01;
mw 0x44e10870 0x30;

mw 0x44e10874 0x08;
mw 0x44e10878 0x08;
mw 0x44e1087c 0x08;
mw 0x44e10880 0x08;
mw 0x44e10884 0x08;
mw 0x44e10888 0x08;
mw 0x44e1088c 0x09;

mw 0x44e10890 0x08;

mw 0x44e10894 0x08;
mw 0x44e10898 0x08;
mw 0x44e1089c 0x08;
md 0x44e10800 40;

md 0x50000060 8;

// config 1 to 7
mw 0x50000060 0x29000000;
mw 0x50000064 0x00020200;
mw 0x50000068 0x22010110;
mw 0x5000006c 0x02016211;
mw 0x50000070 0x01010202;
mw 0x50000074 0x80000000;
mw 0x50000078 0x00000f41;

0 Biser Gatchev-XID over 10 years ago in reply to jithendra kumar

TI__Guru**** 393215 points

Another hardware problem that may be preventing this is the presence of the eMMC on BBB on these lines. You can check the BBB schematic for reference: http://elinux.org/Beagleboard:BeagleBoneBlack#Hardware_Files

0 jithendra kumar over 10 years ago in reply to Biser Gatchev-XID

Prodigy 180 points

Hi,
Thank you for reply. Is there any solution to solve this problem.

0 Biser Gatchev-XID over 10 years ago in reply to jithendra kumar

TI__Guru**** 393215 points

Place the eMMC in reset, but I'm don't know how this can be done. There is a reset line to the eMMC, but I think it needs a command to be sent to eMMC for this line to become active on the eMMC side. You can check on the www.Beagleboard.org forums if somebody has done this. A very crude solution would be to unsolder the eMMC. You can also use a Beaglebone White, if you can find one - it doesn't have an eMMC.

0 jithendra kumar over 10 years ago in reply to Biser Gatchev-XID

Prodigy 180 points

Hi Biser,

As you said, emmc reset pin is enable low,which is connected to GPIO1-20 pin,even I make a GPIO1-20 High ,the GPMC clock is not comming. If you have any idea ,please share .

0 Biser Gatchev-XID over 10 years ago in reply to Biser Gatchev-XID

TI__Guru**** 393215 points

Biser Gatchev-XID said:
There is a reset line to the eMMC, but I think it needs a command to be sent to eMMC for this line to become active on the eMMC side. You can check on the www.Beagleboard.org forums if somebody has done this.

Simply toggling the reset line will not drive the eMMC in reset state. eMMC reset needs to be enabled beforehand.

0 jithendra kumar over 10 years ago in reply to Biser Gatchev-XID

Prodigy 180 points

Hi Biser,

As mentioned by you, by enabling the gpio1_20 pin as high, the eMMC is going to reset. We confirmed it by checking the signal on pin 4 on U3/R162( as per schematic). We are not getting any signals on pins P8_21 (Clock) and P8_26(chip select). Could you please help us to overcome this issue.

0 Biser Gatchev-XID over 10 years ago in reply to jithendra kumar

TI__Guru**** 393215 points

Check your pinmux settings on these pins.

0 jithendra kumar over 10 years ago in reply to Biser Gatchev-XID

Prodigy 180 points

Hi Biser,

These are the pin mux configurations for gpmc after enabled the dts file

group: pinmux_gpmc_pins
pin 0 (44e10800)
pin 1 (44e10804)
pin 2 (44e10808)
pin 3 (44e1080c)
pin 4 (44e10810)
pin 5 (44e10814)
pin 6 (44e10818)
pin 7 (44e1081c)
pin 8 (44e10820)
pin 9 (44e10824)
pin 10 (44e10828)
pin 11 (44e1082c)
pin 12 (44e10830)
pin 13 (44e10834)
pin 14 (44e10838)
pin 15 (44e1083c)
pin 29 (44e10874)
pin 35 (44e1088c) (gpmc _ clock)
pin 36 (44e10890)
pin 37 (44e10894)
pin 38 (44e10898)
pin 39 (44e1089c)
pin 30 (44e10878)
pin 56 (44e108e0)
pin 58 (44e108e8)
pin 57 (44e108e4)
pin 59 (44e108ec)
pin 54 (44e108d8)
pin 55 (44e108dc)
pin 53 (44e108d4)
pin 51 (44e108cc)
pin 52 (44e108d0)
pin 50 (44e108c8)
pin 48 (44e108c0)
pin 49 (44e108c4)
pin 46 (44e108b8)
pin 47 (44e108bc)
pin 44 (44e108b0)
pin 45 (44e108b4)
pin 42 (44e108a8)
pin 43 (44e108ac)
pin 40 (44e108a0)
pin 41 (44e108a4)
pin 33 (44e10884)
pin 32 (44e10880)
pin 28 (44e10870)
pin 31 (44e1087c) (gpmc-csn0)

0 Biser Gatchev-XID over 10 years ago in reply to jithendra kumar

TI__Guru**** 393215 points

jithendra kumar said:
pin 35 (44e1088c) (gpmc _ clock)

This pin is output on P8_18

jithendra kumar said:
pin 31 (44e1087c) (gpmc-csn0)

This pin is output on P8_26

Please read the contents of registers 0x44e1088C and 0x44e1087C and post them.

0 jithendra kumar over 10 years ago in reply to Biser Gatchev-XID

Prodigy 180 points

We are using P8_18 as Gpmc_wait1 (MOde 2) and P8_21 as Gpmc_clk(mode 1).
the values are
44e1088c- 00000029 (gpmc_clk)
44e1087c-00000008 (gpmc_csn0)

0 Biser Gatchev-XID over 10 years ago in reply to jithendra kumar

TI__Guru**** 393215 points

jithendra kumar said:
44e1088c- 00000029 (gpmc_clk)

This pin is named GPMC_CLK. Respective padconf register is conf_gpmc_clk. This pin is in Mode 1. It must be in Mode 0 for GPMC_CLK to be output.

jithendra kumar said:
44e1087c-00000008 (gpmc_csn0)

This pin is named GPMC_CSn0. Respective padconf register is conf_gpmc_csn0. This pin is correctly placed in Mode 0 for GPMC_CSn0 to be output.

jithendra kumar said:
We are using P8_18 as Gpmc_wait1 (MOde 2) and P8_21 as Gpmc_clk(mode 1).

This I don't understand.

0 jithendra kumar over 10 years ago in reply to Biser Gatchev-XID

Prodigy 180 points

As per Beaglebone black SRM ,P8_18 Pin is for GPMC_clk_Mux0 (Mode 0), P8_21 pin is for GPMC_Clk(mode 1). According to that we configured 44e1088c- 00000029 as gpmc_clk

0 Biser Gatchev-XID over 10 years ago in reply to jithendra kumar

TI__Guru**** 393215 points

Pin P8_21 goes to processor pin GPMC_CSn1, which indeed outputs GPMC_CLK in mode 1. But the pinmux register for this pin is conf_gpmc_csn1, at address 0x44E10880.

conf_gpmc_csn1

0 jithendra kumar over 10 years ago in reply to Biser Gatchev-XID

Prodigy 180 points

We are setting the pinmux register for P8_21 at address 0x44e10880 as output in mode 1.

mw 0x44e10880 0x01

0 jithendra kumar over 10 years ago in reply to Biser Gatchev-XID

Prodigy 180 points

Hi Biser,

We did a dts file for GPMC and enabled it.When we saw the pinmux by using command " cat /sys/kernel/debug/pinctrl/44e10800.pinmux/pingroups", it shows like this

group: pinmux_userled_pins

pin 21 (44e10854)
pin 22 (44e10858)
pin 23 (44e1085c)
pin 24 (44e10860)

group: pinmux_rstctl_pins
pin 20 (44e10850)

group: pinmux_i2c0_pins
pin 98 (44e10988)
pin 99 (44e1098c)

group: pinmux_i2c2_pins
pin 94 (44e10978)
pin 95 (44e1097c)

group: pinmux_mmc1_pins
pin 88 (44e10960)

group: pinmux_userled_pins
pin 21 (44e10854)
pin 22 (44e10858)
pin 23 (44e1085c)
pin 24 (44e10860)

group: pinmux_gpmc_pins
pin 0 (44e10800)
pin 1 (44e10804)
pin 2 (44e10808)
pin 3 (44e1080c)
pin 4 (44e10810)
pin 5 (44e10814)
pin 6 (44e10818)
pin 7 (44e1081c)
pin 8 (44e10820)
pin 9 (44e10824)
pin 10 (44e10828)
pin 11 (44e1082c)
pin 12 (44e10830)
pin 13 (44e10834)
pin 14 (44e10838)
pin 15 (44e1083c)
pin 29 (44e10874)
pin 32 (44e10880)
pin 35 (44e1088c)
pin 36 (44e10890)
pin 37 (44e10894)
pin 38 (44e10898)
pin 39 (44e1089c)
pin 56 (44e108e0)
pin 58 (44e108e8)
pin 57 (44e108e4)
pin 59 (44e108ec)
pin 54 (44e108d8)
pin 55 (44e108dc)
pin 53 (44e108d4)
pin 51 (44e108cc)
pin 52 (44e108d0)
pin 50 (44e108c8)
pin 48 (44e108c0)
pin 49 (44e108c4)
pin 46 (44e108b8)
pin 47 (44e108bc)
pin 44 (44e108b0)
pin 45 (44e108b4)
pin 42 (44e108a8)
pin 43 (44e108ac)
pin 40 (44e108a0)
pin 41 (44e108a4)
pin 30 (44e10878)
pin 32 (44e10880)
pin 28 (44e10870)
pin 31 (44e1087c)

The below Adress locations are shown as User led pins.

pin 21 (44e10854)
pin 22 (44e10858)
pin 23 (44e1085c)
pin 24 (44e10860)

But as per SRM these locations serve as A5, A6, A7, A8.

How can I make those pins as gpmc pins

0 Biser Gatchev-XID over 10 years ago in reply to jithendra kumar

TI__Guru**** 393215 points

You must remove the User LED group from your .dts file and add these pins to the GPMC group.

0 jithendra kumar over 10 years ago in reply to Biser Gatchev-XID

Prodigy 180 points

we did not enable led group in our dts file. But, we have configured those pins as GPMC pins in our dts file. Even then, the pin mux lists them as user led pins. How do we make them the GPMC pins

0 Yordan Kovachev over 10 years ago in reply to jithendra kumar

TI__Guru**** 161600 points

Hi,

You need to add those pins inside the gpmc_pins dts node in am335x-boneblack.dts. After that you need to modify the am335x-bone-common.dtsi, in order to remove the user leds pinmux settings & disable the leds device tree node.

Best Regards,
Yordan

0 jithendra kumar over 10 years ago in reply to Yordan Kovachev

Prodigy 180 points

Hi Yordon,

Actually we degraded the Kernel version from 3.14 to 3.8, so the am335x-bone-common.dtsi files are in the path " /opt/source/dtb-3.14-ti/src/arm/" .As you said I commented the LED group portion in am335x-bone-common.dtsi, saved it and we rebooted the device. But, even then the leds are glowing and pinmux also shows them as user led group. Can you let us know how to disable these pins such that, we can make them visible in our pinmux as gpmc pins.

0 Yordan Kovachev over 10 years ago in reply to jithendra kumar

TI__Guru**** 161600 points

Hi,

Can you share the repository, from which you've downloaded the 3.8 kernel sources? The 3.8 sources I have also use the arch/arm/boot/dts folder to store the dts & dtsi files.

Also I am a little confused from:

jithendra kumar said:
Actually we degraded the Kernel version from 3.14 to 3.8, so the am335x-bone-common.dtsi files are in the path " /opt/source/dtb-3.14-ti/src/arm/" .As you said I commented the LED group portion in am335x-bone-common.dtsi, saved it and we rebooted the device

What I meant was modify the kernel sources & rebuild the kernel (or at least the dts..) & flash your device with the new images. Kernel does not use dts or dtsi files; those are source files. After you build the kernel/device tree you will have an am335x-boneblack.dtb generated and upon booting u-boot will load this dtb file and the kernel will use it to initialize the device pads & peripherals.

Best Regards,

Yordan

0 jithendra kumar over 10 years ago in reply to Yordan Kovachev

Prodigy 180 points

Hi Yordan,

Actually, We didnt build the kernel source.Instead we used prebuilt Debian image dated 26-4-2015 downloaded from the website. This Image had 3.14 kernel.

Since we wanted Capemanger support,we downgraded the kernal to 3.8 using these commands from github.com/.../Capemgr

sudo apt-get update
sudo apt-get install linux-image-3.8.13-bone68

Now we created our own dts file for GPMC configuration, Compiled using DTC compiler and  placed the .dtbo file in /lib/firmware .
 then we enabled the dtbo file by using the command

"$ echo BB-BONE-GPMC >/sys/devices/bone_capemgr*/slots"

Now our Pinmux shows all our gpmc pins configurations except the USR Led pins(p8-42,P8-39,P8-40,P8-27) and Emc Reset pin(P8-41)
After your earlier reply we modified the am335x-bone-common.dtsi file and rebooted,  even after this there is no change

Do we need to generate the dtbo file for the dtsi ,if yes where do we need to place it such that the board boots up with our modified configuration .

0 Yordan Kovachev over 10 years ago in reply to jithendra kumar

TI__Guru**** 161600 points

Hi,

jithendra kumar said:
After your earlier reply we modified the am335x-bone-common.dtsi file and rebooted, even after this there is no change

Do we need to generate the dtbo file for the dtsi ,if yes where do we need to place it such that the board boots up with our modified configuration .

No it shouldn't be necessary to generate dtb file for am335x-bone-common.dtsi; this file is like a header, it is included in the am335x-boneblack.dts with the following line:

#include "am33xx.dtsi"

#include "am335x-bone-common.dtsi"

However this is for ti sdk kernel, verify for your linux kernel version. You may have other dts/dtsi files included, check their content and modify if necessary.

Then build the .dtb file.

As for where to place the generated .dtb file, in my setup they are placed at /boot along with the kernel zImage.

Best Regards,

Yordan

0 jithendra kumar over 10 years ago in reply to Yordan Kovachev

Prodigy 180 points

Hi Yordan,

We were able to sort out the issue of user led pins. We actually, decompiled the am335xx-boneblack.dtb file present in the /boot/dtbs/3.8. directory. Then, we modified led portion and compiled the dtb.

But, now we have another issue where in, when we try to access the chip select base address 0x01000000 through our application, we get the bus error. Do we need to do the GPMC configuration for the CONFIG REGISTERS 1 to 7 in the dts file itself or do it in our application by using mmap?

Regards,

Jithendra

0 Yordan Kovachev over 10 years ago in reply to jithendra kumar

TI__Guru**** 161600 points

Hi,

You need to mmap() the address space of the chip select from your application if it is user space api. If it is a kernel source you need to use the ioremap().

Best Regards,
Yordan

0 jithendra kumar over 10 years ago in reply to Yordan Kovachev

Prodigy 180 points

Hi Yordan,

We have mmap the GPMC Configuration registers:
uint gpmc_init()
{
ushort csNum = 0;
uint temp = 0;
int fd = -1;

fd = open("/dev/mem", O_RDWR|O_SYNC); //O_SYNC makes the memory uncacheable
if(fd == -1)
{
printf("Unable to open the memory for GPMC Configurations\n");
return UNABLE_TO_OPEN_FILE;
}

__mmapl = (ulong*) mmap(NULL, 0x20000000, PROT_READ|PROT_WRITE, MAP_SHARED, fd, MMAP_OFFSET);

HWREG(SOC_CM_WKUP_REGS + 0x007c)|= 0x00001100; //mw 0x44e0047C 0x00001100 for CM_WKUP register - CM_CLKDCOLDO_DPLL_PER
HWREG(SOC_CM_DPLL_REGS + 0x20)|= 0x01;//mw 0x44e00520 0x01 for CM_DPLL register - CM_CPTS_RFT_CLKSEL
HWREG(SOC_CONTROL_REGS + 0x0444)|= 0x01;//mw 0x44e10444 0x01 for register - clk32kdivratio_ctrl
HWREG(SOC_PRCM_REGS + 0x04)|= 0x00;//mw 0x44e00004 0x00; for CM_PER register - CM_PER_L3S_CLKSTCTRL
//enable clock to GPMC module
HWREG(SOC_PRCM_REGS + CM_PER_GPMC_CLKCTRL ) |=
CM_PER_GPMC_CLKCTRL_MODULEMODE_ENABLE;//mw 0x44e00030 0x02 for CM_PER register - CM_PER_GPMC_CLKCTRL

//check to see if enabled
while((HWREG(SOC_PRCM_REGS + CM_PER_GPMC_CLKCTRL) & CM_PER_GPMC_CLKCTRL_IDLEST) !=
(CM_PER_GPMC_CLKCTRL_IDLEST_FUNC << CM_PER_GPMC_CLKCTRL_IDLEST_SHIFT));

//HWREG(0x4804c134) = 0x00;//mw 0x4804c134 0x00 of L4_PER register - GPIO1 - GPIO-OE
//HWREG(0x4804c194) = 0x00100000;//mw 0x4804c194 0x00100000 of L4_PER register - GPIO1 - GPIO-SETDATAOUT

//reset the GPMC module
HWREG(SOC_GPMC_0_REGS + GPMC_SYSCONFIG ) |= GPMC_SYSCONFIG_SOFTRESET;
while((HWREG(SOC_GPMC_0_REGS + GPMC_SYSSTATUS) & GPMC_SYSSTATUS_RESETDONE) ==
GPMC_SYSSTATUS_RESETDONE_RSTONGOING);

HWREG(SOC_GPMC_0_REGS + GPMC_SYSCONFIG) = 0x00000010;//mw 0x50000010 0x0000000A; - GPMC-SYSCONFIG

HWREG(SOC_GPMC_0_REGS + GPMC_TIMEOUT_CONTROL) = 0x00001FF1;//mw 0x50000040 0x1ff1;//time out control

HWREG(SOC_GPMC_0_REGS + GPMC_CONFIG1(csNum)) = 0x29000003;//mw 0x50000060 0x29000003;
HWREG(SOC_GPMC_0_REGS + GPMC_CONFIG2(csNum)) = 0x00020200;//mw 0x50000064 0x00020200;
HWREG(SOC_GPMC_0_REGS + GPMC_CONFIG3(csNum)) = 0x22010110;//mw 0x50000068 0x22010110;
HWREG(SOC_GPMC_0_REGS + GPMC_CONFIG4(csNum)) = 0x02016211;//mw 0x5000006c 0x02016211;
HWREG(SOC_GPMC_0_REGS + GPMC_CONFIG5(csNum)) = 0x01010202;//mw 0x50000070 0x01010202;
HWREG(SOC_GPMC_0_REGS + GPMC_CONFIG6(csNum)) = 0x80000000;//mw 0x50000074 0x80000000;
HWREG(SOC_GPMC_0_REGS + GPMC_CONFIG7(csNum)) = 0x00000f41;//mw 0x50000078 0x00000f41;

munmap((void*) MMAP_OFFSET, 0x20000000);
if (fd != -1) {
close(fd);
}

return 0;
}

And our main function is as follows:
#define MMAP_OFFSET 0x44c00000

// redefine HWREG macro to use MMAP result
#define HWREG(x) __mmapl[(x-MMAP_OFFSET)/4]

int main(int argc, char** argv)
{
int i, k;
int j=0;
ushort *extmem;
ushort temp;

int fd = open("/dev/mem", O_RDWR|O_SYNC); //O_SYNC makes the memory uncacheable
__mmapl = (ulong*) mmap(NULL, 0x20000000, PROT_READ|PROT_WRITE, MAP_SHARED, fd, MMAP_OFFSET);

gpmc_init();

extmem = (ushort*) mmap((void *)0x01000000, 0x400, PROT_READ|PROT_WRITE, MAP_SHARED, fd,0x09000000);

for (i = 0; i<0x400; i++)
{

extmem[i] = 0xaa;
mymem[i] = 0xaa;
printf("%x %x\n", temp, mymem[i]);

}
return 0;
}

Even after this, we are getting bus error. Could you please look at our GPMC configurations?

Regards,
Jithendra
Jithe

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