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C6670 External clocks and SYSCLKs

Hari..
Intellectual 605 points

Hi,


In  C6670 datasheet (SPRS689D Page 129,130) it says that SYSCLK3 is used to clock DDR3EMIF and SYSCLK10 for SRIO. But there are external clocks for DDR3(DDRCLKN) and SRIO (SRIOSGMIICLK).

1. What happens to the external clocks if SRIO and DDR3 SYSCLK registers are programmed with divider values?

2. What are the priorities for SYSCLK and external clock ?

Thanks

Hari

  • 0
    TI__Mastermind 42545 points

    Hi Hari,
    The clocking diagram you are referring to defines the internal clocking needed to synchronize communications between the IPs and the DSP cores. These clocks are based on the output of the main PLL which is driven by the SYSCLKP/N. The DDRCLKP/N clock is used to drive the DDR PLL and used by the DDR PHYs to generate the DDRCLKOUT signals. The SRIOSGMIICLK is used by both the SGMII and SRIO serdes PHYs.
    CORECLK and DDRCLK are required for all C6670 designs. The SRIOSGMIICLK is required if either the SGMII or the SRIO interfaces are used.
    Regards,
    Bill

  • 0 in reply to Bill Taboada
    Intellectual 605 points
    Hi Bill,

    Thank you!! Still I am not that clear.
    So in the DDR3 case, DDRCLKP/N clock drives the physical DDR3 device and the SYSCLKP/N drives the DDR3 memory controller. Is that right ?

    And SYSCLK7 is used as input for UART. Can you explain how the SYSCLK7 works for UART. Is there any document to trace the path of SYSCLK7 which is input to UART clock generation (SPRUGP1 Figure 2-1) ?

    Thanks
    Hari
  • 0 in reply to Hari..
    TI__Mastermind 42545 points

    Hi Hari,

    You are partially correct concerning the DDRCLKP/N. The DDR controller has a division where the data must transition from the internal TeraNet and MSMC, which is clocked by the SYSCLK, to the DDR3 interface, which is clocked by DDRCLK. It is not important where that transition occurs but it is necessary that both clocks exist. The portion of the DDR3 controller that initiates the DDR3 IOs requires the DDRCLK. This is why that clock must be present even if the DDR3 interface is not used.

    SYSCLK7 is a simple divide down from the output of the main PLL. This is shown in figure 7-7 in the data manual. The output of the main PLL is divided by 6 to create SYSCLK7 and that clock is used as a source for the UART IP.

    Regards,

    Bill