The AM335x data sheet specifies the TSC_ADC sampling rate of typical 200ksps for an ADC Clock of 3MHz (Table 5-16).
However TRM defines a maximum ADC clock rate of 24MHZ (12.2.2, Table 12-2).
Is it possible to get a higher sampling rate than 200ksps with a higher ADC clock? Is there any influence on accuracy when clock is increased?
I am aware that the throughput of the internal bus may not be able to support higher sustained rates than 200ksps. What I need is only a short sequence (3-4) of acquisitions within a vers short time period, which could be handled by the TSC_ADC FIFO. Repetition rate of this fast sampling is in the 100us range, so absolute throughput is not an issue.
