AM3352 + DP83848 PHY RMII mode

Hello,

I'm having problem getting the DP83848 PHY to work in RMII mode.  I saw several posts with people having this problem but some did not post the solution on how they resolved it and some posts are now dead.  Any help would be great.

In /board/ti/am335x/mux.c

static struct module_pin_mux rmii1_pin_mux[] = {
    {OFFSET(mii1_crs), MODE(1) | RXACTIVE},        /* RMII1_CRS */
    {OFFSET(mii1_rxerr), MODE(1) | RXACTIVE},    /* RMII1_RX_ERR */
    {OFFSET(mii1_txen), MODE(1)},                /* RMII1_TX_EN */
    {OFFSET(mii1_rxdv), MODE(1) | RXACTIVE},    /* RMII1_RX_DV */
    {OFFSET(mii1_txd1), MODE(1)},                /* RMII1_TD1 */
    {OFFSET(mii1_txd0), MODE(1)},                /* RMII1_TD0 */
    {OFFSET(mii1_rxd1), MODE(1) | RXACTIVE},    /* RMII1_RD1 */
    {OFFSET(mii1_rxd0), MODE(1) | RXACTIVE},    /* RMII1_RD0 */
    {OFFSET(rmii1_refclk), MODE(0) | RXACTIVE},    /* RMII1_REF_CLK */
    {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */
    {OFFSET(mdio_clk), MODE(0) | PULLUP_EN},    /* MDIO_CLK */
    {-1},
};

void enable_board_pin_mux(struct am335x_baseboard_id *header)
{
        configure_module_pin_mux(i2c1_pin_mux);
        configure_module_pin_mux(rmii1_pin_mux);
        configure_module_pin_mux(mmc1_pin_mux);
}

In /include/configs/am335x_evm.h

/* Network. */
#define CONFIG_PHY_GIGE
#define CONFIG_PHYLIB
#define CONFIG_PHY_NATSEMI

In /drivers/net/phy/natsemi.c

static int dp83848_config(struct phy_device *phydev)
{
    int mii_reg;
    u32 phyId;

    mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_PHYSID1);
    phyId = (mii_reg & 0xffff) << 16;
    mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_PHYSID2);
    phyId |= (mii_reg & 0xffff);
    printf("%s uid:%08X\n", phydev->drv->name, phydev->drv->uid);

    phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET);

    genphy_config_aneg(phydev);

    return 0;
}

static struct phy_driver DP83848_driver = {
    .name = "NatSemi DP83848",
    .uid  = 0x20005C90,
    .mask = 0x3FFFFFF0,
    .features = PHY_BASIC_FEATURES,
    .config = &dp83848_config,
    .startup = &genphy_startup,
    .shutdown = &genphy_shutdown,
};

int phy_natsemi_init(void)
{
    phy_register(&DP83848_driver);
    return 0;
}

In /board/ti/am335x/board.c

static struct cpsw_slave_data cpsw_slaves[] = {
    {
        .slave_reg_ofs    = 0x208,
        .sliver_reg_ofs    = 0xd80,
#ifdef CONFIG_PHY_NATSEMI
        .phy_addr    = 1,
#else
        .phy_addr = 0,
#endif
    },
    {
        .slave_reg_ofs    = 0x308,
        .sliver_reg_ofs    = 0xdc0,
        .phy_addr    = 1,
    },
};

writel((RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE), &cdev->miisel);
            cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RMII;
            cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RMII;
            puts("eth: PHY-RMII\n");

In /arch/arm/include/asm/arch-am33xx/cpu.h

* gmii_sel register defines */
#define GMII1_SEL_MII        0x0
#define GMII1_SEL_RMII        0x1
#define GMII1_SEL_RGMII        0x2
#define GMII2_SEL_MII        0x0
#define GMII2_SEL_RMII        0x4
#define GMII2_SEL_RGMII        0x8
#define RGMII1_IDMODE        BIT(4)
#define RGMII2_IDMODE        BIT(5)
#define RMII1_IO_CLK_EN        BIT(6)
#define RMII2_IO_CLK_EN        BIT(7)
#define MII1_IO_CLK_EN        0x1

#define MII_MODE_ENABLE        (GMII1_SEL_MII | GMII2_SEL_MII)
#define RMII_MODE_ENABLE     (GMII1_SEL_RMII | GMII2_SEL_RMII)
#define RGMII_MODE_ENABLE    (GMII1_SEL_RGMII | GMII2_SEL_RGMII)
#define RGMII_INT_DELAY        (RGMII1_IDMODE | RGMII2_IDMODE)
#define RMII_CHIPCKL_ENABLE     (RMII1_IO_CLK_EN | RMII2_IO_CLK_EN)

Sorry for the code paste. But am I missing something?