C6474 SRIO to FPGA under DSP BIOS v6

I found one more difference, the stand-alone version ran (completely) in L2 cache (0x10880000) and the DSP BIOS vesion ran out of RAM (0x80000000)

when I forced the src/dst of the SRIO data xfer into L2 cache it (MAINT_RD) works under DSP BIOS too. Can anyone shed light on that? Is SRIO DMA limited to L2 cache (although the MAINT_WR were successful from RAM)

So now I have a ccsv4/ DSP BIOS v6 question... How do I specify a section into L2 cache? ...

#pragma DATA_SECTION(mybuf, ".l2ram"); // puts mybuf into a section called ".l2ram"

but the only way I know to put the section ".l2ram" into the L2RAM address space is via the linker.cmd which is genarated dynamically for DSP BIOS projects

When you say L2 cache, I assume you actually mean L2 SRAM (i.e part of L2 used as SRAM). As far as I know, SRIO DMA should be able to move data to/from any memory that DSP can address. When you look through CCS memory window and uncheck the L2 and L1 boxes (so that you don't see cached data, you see external memory), do you see the external memory updated after when you think transfer is complete? Also, you can modify the stand-alone version to use external memory and see if it works, to make sure your base is o.k. Note that L1D cache is not coherent with external memory, so you may need write back and invalidate operations in your code if you want to use external memory.

In CCSv4, you will need to create a platform file through RTSC project to customize memory map. Type "how to create memory map" in CCS help and look at two flash videos, one on RTSC platform wizard and related one of customizing memory sections. Reading up the BIOS 5 to 6 migration guide in the BIOS docs folder would be useful. You will need to spend some time to learn/practice this if you haven't done it before.

yes I meant L2 SRAM.

I followed the flash video example to create a memory map, since then my app corrupts itself and crashes. I created a new project and the new one crashes the same way. obviously, I messed something up very badly. I get : "Exception abort! Check Exception Log for details" ... no log to be found, but I have to re-load the app to retry. (.text is trashed)

the video had me create a new repository, which I created outside the workspace. I've since renamed the directory of the new repository, but still all my (previously working) bios projects trash themselves.

At a loss...

I had a host of problems, and I'm finally mostly working, but I still haven't solved my custom memory map issue...

for a non-DSP/BIOS project, I can create a link.cmd file that looks like this:

MEMORY

{

L2SPECIAL: o=0x10880000 l=0x001effff

SDRAM: o=0x80000000 l=0x00800000

}

SECTIONS:

{

 .text > SDRAM

.data > SDRAM

.bss > SDRAM

.myspecial > L2SPECIAL

}

and C code that does a:

#pragma DATA_SECTION(mybuf, ".myspecial");

struct tag mybuf[NUMBUF];

but for a RTSC project, I do not know how to accomplish this. Following the flash demo you told me about I can now add the "L2SPECIAL: o=0x10880000 l=0x001effff" line into the MEMORY area, and, via the "#pragma..." I can make my C symbol "mybuf" go into the ".myspecial" section, but I'm still missing how to add the line ".myspecial > L2SPECIAL" into the SECTIONS block.

TIA

dkerns,

Just out of curiosity, what FPGA are you using and how are you handling the packets inside of it? Is this with the Xilinx provided SRIO IP core or something you developed yourself?