I am trying to get SPI to work on the jac5eco board (jacinto 5).
First I used the test setting (SYST), put the module into test mode, hooked the output to an oscilloscope and toggled the chip select signal to see if I could get something out at all. That worked.
Now I have tried to set up as basic a transmit case that I can but it is not working as expected, the chip select never happens.
However the transmission done bit (EOT) gets set. The manual however also says I should check the bit TXS in the CHxSTAT reg.
From manual:
"Wait until end of transfer? MCSPI_CHxSTAT[2:1] = 0x2"
EOT is bit 2 and TXS is bit 1.
When reading the register the value is 6 which means TXS is also set which means register is empty.
I find the info here a bit hard to read, isn't that actually correct?
Is it also correct that the TXS and RXS bit mean different things, 0 is full for one and empty for the other or is that an error in the manual?
From the jac5eco manual, SPRUHF4C_DRA62x, this is the procedure for setup and transmit:
void Spi_Hw_Init( const Spi_ConfigType *ConfigPtr )
{
uint32 resetDone = FALSE;
mapHwRegs();
for (uint32 i = 0; i < SPI_NBR_HW_UNITS; i++)
{
*(Spi_HwRegs[i].MCSPI_SYSCONFIG) |= (MCSPI_SOFTRESET << MCSPI_SOFTRESET_OFFSET);
}
#ifdef DEBUG_CHECK_SETUP
uint32 regValPreSYS, regValPreMODCTL;
regValPreSYS = *Spi_HwRegs[1].MCSPI_SYSCONFIG;
regValPreMODCTL = *Spi_HwRegs[1].MCSPI_MODULCTRL;
#endif
while (!resetDone)
{
resetDone = 1;
for (uint32 i = 0; i < SPI_NBR_HW_UNITS; i++)
{
resetDone &= ((*(Spi_HwRegs[i].MCSPI_SYSSTATUS) & MCSPI_RESETDONE_MASK) ==
MCSPI_RESETDONE_MASK);
}
}
for (uint32 i = 0; i < SPI_NBR_HW_UNITS; i++)
{
Spi_Hw_InitController(i);
}
for (uint32 j = 0; j < SPI_EXT_DEVICES_CNT; j++)
{
setupExternalDevice(&ConfigPtr->SpiExternalDevice[j]);
}
#ifdef DEBUG_CHECK_SETUP
uint32 regValPostSYS, regValPostMODCTL;
regValPostSYS = *Spi_HwRegs[1].MCSPI_SYSCONFIG;
regValPostMODCTL = *Spi_HwRegs[1].MCSPI_MODULCTRL;
#endif
}
void Spi_Test_Transmit(void)
{
/* SPI Transmit Mode Initialization */
/* Transmit mode and word length. */
Spi_HwRegs[1].MCSPI_CHn[0].MCSPI_CHnCONF |= (
(MCSPI_TRM_TRANSMIT_ONLY_MODE << MCSPI_TRM_OFFSET) |
(8 << MCSPI_WL_OFFSET)
);
/* Master already set so need to do it again. */
//*Spi_HwRegs[1].MCSPI_MODULCTRL |= (0 << MCSPI_MS_OFFSET);
/* Enable channel. */
MCSPI_CHAN_ENABLE(Spi_HwRegs[1].MCSPI_CHn[0]);
/* Channels activated low during active state (EPOL) */
Spi_HwRegs[1].MCSPI_CHn[0].MCSPI_CHnCONF |= (1 << 6);
/* Clock held high during active state (POL) */
Spi_HwRegs[1].MCSPI_CHn[0].MCSPI_CHnCONF |= 0 << 1;
/* Data latched on odd-numbered edges of the SPI clock */
Spi_HwRegs[1].MCSPI_CHn[0].MCSPI_CHnCONF |= 0 << 0;
/* Reset the status bits. */
// Datasheet actually write 1 to reset so here is a contradiction.
*Spi_HwRegs[1].MCSPI_IRQSTATUS = 0;
/* Transmit-Only Procedure – Polling Method */
uint32 statRegVal = Spi_HwRegs[1].MCSPI_CHn[0].MCSPI_CHnSTAT;
uint32 txReg = Spi_HwRegs[1].MCSPI_CHn[0].MCSPI_TXn;
// Put the data in the tx reg
Spi_HwRegs[1].MCSPI_CHn[0].MCSPI_TXn = 0xA5A5A5A5;
/* Start the channel. (Already done...) */
MCSPI_CHAN_ENABLE(Spi_HwRegs[1].MCSPI_CHn[0]);
statRegVal = Spi_HwRegs[1].MCSPI_CHn[0].MCSPI_CHnSTAT;
txReg = Spi_HwRegs[1].MCSPI_CHn[0].MCSPI_TXn;
while ((Spi_HwRegs[1].MCSPI_CHn[0].MCSPI_CHnSTAT & 6) != 4)
{
statRegVal = Spi_HwRegs[1].MCSPI_CHn[0].MCSPI_CHnSTAT;
txReg = Spi_HwRegs[1].MCSPI_CHn[0].MCSPI_TXn;
};
MCSPI_CHAN_DISABLE(Spi_HwRegs[1].MCSPI_CHn[0]);
while (1) {};
}
