C67x : flow control with uPP interface ?

lavenu patrick1

Hello,

I'm using uPP interface with a C6748.

My DSP communicate with an FPGA the FPGA is faster than DSP and i would like my FPGA to transfert data to my DSP only when it is ready to receive them.

Could you tell me how could I realize a flow control from FPGA to DSP ? is it possible to drive the WAIT signal ?

thank you very much in adance for your help.

Pat.

over 10 years ago

0 Titusrathinaraj Stalin over 10 years ago

TI__Guru** 116100 points

Hi,
In which mode, you are operating the uPP ?
Transmit mode or receive mode ?
I hope, uPP is operating as receive mode.
If uPP (DSP) is operating as receive mode then we can configure WAIT pin for FPGA to wait while transmitting data.
We need to assert the WAIT pin for not to send any data to DSP through uPP from FPGA.
Also, please refer to the following relevant uPP TI wiki pages.

processors.wiki.ti.com/.../Introduction_to_uPP
processors.wiki.ti.com/.../BIOS_Driver
processors.wiki.ti.com/.../Using_the_uPP_EVM_example_applications_from_the_BIOS_PSP

0 lavenu patrick1 over 10 years ago in reply to Titusrathinaraj Stalin

Intellectual 600 points

Thank you very much for your answer. Yes the DSP is in the receive mode.
However, I think that I can not manage the WAIT signal by myself (DSP application) ?if yes , how could I do that ?
In other words , does some uPP signal could be used by the application to realize a flow control ?
The internal DMA controller does not support automatically reloading DMA transfer descriptors , what happened to the data send by the FPGA if the DSP hasn't enough time to program a new DMA ? are they store in a FIFO or are they lost ?
Thank you for your help.

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C67x : flow control with uPP interface ?