• State TI Thinks Resolved
  • Locked Locked
  • Replies 4 replies
  • Answers 1 answer
  • Subscribers 98 subscribers
  • Views 900 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

uPP receipt problem with C6748 when burst of data too closed

lavenu patrick1
Intellectual 600 points


Hello,

I'm using uPP interface  in C6748 processor.  The DSP is receiving data from a FPGA.

I would like to know how the uPP component in DSP side managed the fact that the FPGA can send 2 bursts of data very closely ( 100 ns for example) ? does the uPP (DSP side) support it ? are there some constraints of timing limitation between 2 bursts ? where could be the limitation ?

Thank you in advance for your answer.

Pat.

  • 0
    TI__Mastermind 43660 points
    Hello Laven,

    Yes, the uPP supports data burst using DMA.

    What is the burst size you are sending from FPGA ? There is a limitation on the burst length through DMA. Please refer section 31.2.4 Internal DMA Controller Description and later topics in the device TRM for more detailed explanation on this.

    You could also find the below threads which are relevant to the uPP data burst.

    e2e.ti.com/.../859579

    e2e.ti.com/.../320936

    e2e.ti.com/.../473681


    Regards,
    Senthil
  • 0 in reply to Senthilkumar Srinivasan
    Intellectual 600 points
    Thank you for your answer, the burst size is 4 bytes, the duration between the 2 bursts is 500 ns. the uPP is working at 50 Mhz.
    I programmed a DMA and queued an other so normally the uPP is able to receive the second burst without soft interaction.
    I received only an interrupt OEW for one burst , it looks like the other burst is lost .
    Any suggestion ? thank you for your help.
    Pat.
  • 0 in reply to lavenu patrick1
    TI__Guru** 116100 points
    Hi,
    You meant that able to get all the interrupts with soft interaction.
    Did you check the status registers to know the status of transfer ?
    Able to see the correct behavior when you increase the duration between bursts ?
    Also please make sure that you have enabled the required interrupts.
  • 0 in reply to Titusrathinaraj Stalin
    Intellectual 600 points
    Hi Titus,

    Thank you very much for your help.

    I think that i understood what happened now . After all, the 2 nd burst was actually received in my buffer but not where I thought.

    My problem is that I would like that my 2 nd burst which is beginning with a start signal was saved in the second queued DMA and not in the first DMA. That is to say that regardless of the number of byte count that I programmed the DMA when the FPGA send me a second burst, the uPP component from the DSP send me an EOW and begin to fill the 2nd DMA .

    In summary, is it possible to program the uPP component to rise an EOW interrupt for each burst regardless of the number of byte count programmed for a DMA ?

    Thank you in advance for your answer.

    regards.

    Pat.