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CRC Module configuration issue

Ujjwal Gupta51
Prodigy 130 points

Hi,

We are using BCP for accelerating PDCCH and we are processing per dci to the BCP.We are facing problem when we check the o/p is not as same calculated by software .

Following parameter configred for CRC.Also we are referencing the ti PDSCH sample code for it:-

pCrcHdrCfg->num_scramble_sys=   0;

pCrcHdrCfg->bit_order       =   1; 

 pCrcHdrCfg->dtx_format = 0;

pCrcHdrCfg->method2_id = 0;-->we are just checking CRC o/p before scrambling

 pCrcHdrCfg->local_hdr_len       =   3;

pCrcHdrCfg->va_blk_len      =  27--->according to dci bit(while min tb length should be 40 please confirm )

 pCrcHdrCfg->va_blks     =   1;

 pCrcHdrCfg->va_crc      =   Bcp_CrcFormat_Crc16;

 

input data id 0C89DE3, after BCP processing the data receieved is 425E 0C89DE3 while it should be  1256 0C89DE3 .

can you please help here if anything should configured for PDCCH in CRC.

 

Regards,

Ujjwal

 

  • 0
    TI__Guru* 81335 points

    Welcome to the TI E2E forum. I hope you will find many good answers here and in the TI.com documents and in the TI Wiki Pages (for processor issues). Be sure to search those for helpful information and to browse for the questions others may have asked on similar topics (e2e.ti.com). Please read all the links below my signature.

    Please share the DSP Part number, EVM or Custom Board, Example project & MCSDK version etc.

    Thank you for your patience.

  • 0 in reply to Raja
    Prodigy 130 points
    Hi,
    We are using EVM. DSP C6670.
    MCSDK version : mcsdk_2_01_02_06

    Ujjwal
  • 0 in reply to Raja
    Prodigy 130 points
    and to add on, we are trying to run this on simulator.
    CCS v5.5.0
  • 0 in reply to Ujjwal Gupta51
    TI__Guru* 81335 points
    Hi,
    We recommend you to test the example project on EVM. The simulator support is de-focused. Thank you.
  • 0 in reply to Raja
    TI__Mastermind 30405 points

    Hi Ujjwal,

    Can you please provide the following information for the BCP input packet?

    1. BCP Header Descriptor (input CPPI descriptor hosting the BCP header).
    2. BCP Input Header Buffer (complete BCP header including any Protocol specific Info and/or User Info fields).
    3. BCP Payload descriptor (input CPPI descriptor, linked to the header descriptor, hosting the BCP input payload).
    4. BCP Payload Buffer.
    5. BCP Output descriptor and output buffer.

    In case your setup uses a single input buffer (and descriptor) to supply both the BCP header and payload, we'll have only one BCP Input descriptor and BCP Input buffer (Header + Payload) so please provide the data accordingly.

    Please save the completely formed BCP header and data buffer (from CCS memory window) right before it is sent to the BCP. And as Raja suggested, please run this on an EVM.

    Thanks
    -Nitin

  • 0 in reply to Nitin Sakhuja
    Prodigy 130 points

    Hi Nitin,

    Many thanks for your quick reply.
    I would like to inform you that the issue has been resolved successfully. The BCP Header Descriptors and Payload Descriptor etc were all perfectly configured. The problem was that BCP (for CRC) accepts data in reverse order,i.e., a0 as L.S.B. and a7 as M.S.B. and we couldn't identify this issue until observed in CCS.

    Thanks again for the help.

    Regards

    Ujjwal