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QDMA transfer issue with L2RAM

Thomas Rakesh
Intellectual 390 points

Hi All,

Was the problem resolved?Even we are facing same issue.In Core number 3,QDMA from L2 RAM to DDR is successful. But In Core number 2, QDMA from L2 RAM to DDR/MSMCRAM is wrong.The destination is all 0's.
The multicore DSP is TI 6608.

Please help.

Thanks and Regards,

Thomas

  • 0
    TI__Mastermind 35645 points
    Hi,

    I believe you haven't pointed on the old thread reference which you are talking about? Anyway, what was the problem and which issue you are talking about? What is your QDMA PaRAM set configuration and are you using simultaneous multicore QDMA transfer from L2RAM to DDR? Kindly describe your problem else provide us the thread reference context which you are talking about.

    We would be glad to help you out.

    Thanks & regards,
    Sivaraj K
  • 0 in reply to Sivaraj Kuppuraj
    Intellectual 390 points
    Im sorry about that old thread reference.I just replied to some thread posted "qdma can't access on chip memory ( L2 RAM)".. Issue faced now is is: In Core number 3,QDMA from L2 RAM to DDR is successful. But In Core number 2, QDMA from L2 RAM to DDR/MSMCRAM is wrong.The destination is all 0's.
    Tried all uEdma3Instance =0,1,2 in QdmaLinkChainRun(uEdma3Instance, uQdmaLinkChId); There is only single QDMA transfer ,no other threads/ core is initiating any edma transfer at that instant.
  • 0 in reply to Thomas Rakesh
    TI__Mastermind 35645 points

    Hi,

    Thanks for your update.

    Did you start from our EDMA3 LLD examples or are you writing your own drivers?

    Please check the QDMA channel based transfer code, which is using EDMA3 LLD.

    C:\ti\edma3_lld_02_11_05_02\examples\edma3_driver\src

    The best place is to start with the EDMA CSL example source code has portion of the global/shadow region setup for both EDMA/QDMA channel setup, which could be a good reference:

    C:\ti\pdk_C6678_1_1_2_6\packages\ti\csl\example\edma\edma_test.c

    You can take this as a reference code and modify the same accordingly to trigger interrupts and use shadow regions seperately to support multiple core EDMA transfer.

    Please ensure to use different TCC values for different cores on memory_transfer()  and in order to initialize the transfer simulataneously on multiple cores, you may need to use different TCC values which associates different QDMA channels/bit positions to indicate the transfer completion on the same.

    Also, Kindly ensure the following

    Each core is copying to and from different memory locations (no overlap)

    Each core uses a different channel

    Each core uses a different shadow region

    Each core generates a different EDMA interrupt

    Look at all of the error-related EDMA3 registers, especially QSER and QEMR and ensure there were no missed events or errors.

    Thanks & regards,

    Sivaraj K

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