GPIO interrupt - problem with kernel APIs

ranchu

Guru 20755 points

Hello,

I am having some difficulties in triggering interrupt on DM8148 with kernel APIs.

I am trying to trigger interrupt in gpio 42.

1. all function return correcly.

2. with sysfs I have success, but fails when using kernel APIs.

3. I have attached my code (for both sysfs and kernel APIs)

If anyone have any example, can you please share ?

https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/791/shared.7z

I have also noticed that on calling request_irq the interrupt register (interrupt for GPIO1 bank) , 0x4804C034, value changes from 0 to 0x400 (seems like pin 42 interrupt is enabled). Do I need to set some other registers too ?

I really have no more clues, please help.

Thank you,

Ran

over 10 years ago

0 Pavel Botev over 10 years ago

TI__Guru**** 170625 points

Ran,

Are you aligned with the below wiki page?
processors.wiki.ti.com/.../TI81XX_PSP_GPIO_Driver_User_Guide

Note also that interrupt should be also enabled from the Cortex-A8 ARM Interrupt Controller side.

BR
Pavel

0 ranchu over 10 years ago in reply to Pavel Botev

Guru 20755 points

Hi Pavel,

Yes, I am (the code I'm using as attached to the first message above).
I don't yet understand why it does not work with kernel APIs and only work with sysfs.

Thank you,
Ran

0 ranchu over 10 years ago in reply to ranchu

Guru 20755 points

Hi Pavel,

I see when using kernel APIs that also GPIO41 output pin is not functioning correctly (which does works with sysfs....), while lower GPIO18, 19 , works just fine.
Is it maybe related to some BANK 1 enabling ? How should I enable GPIO for that bank ?

Thank you,
Ran

0 Pavel Botev over 10 years ago in reply to ranchu

TI__Guru**** 170625 points

Ran,

GPIO41 is GP1[9] signal (physical pin V1 or AE17). If you are using V1 physical pin, there is some more info should be considered, see datasheet, Table 3-11. GP1 Terminal Functions

See also TRM, section 3.1.2.2 Special Muxing of GPIO1[7:10] Signals

GP1[9] belongs to GPIO1 module (bank 1) and should be enabled from register CM_ALWON_GPIO_1_CLKCTRL[1:0] MODULEMODE = 0x2

BR
Pavel

0 ranchu over 10 years ago in reply to Pavel Botev

Guru 20755 points

Thank you Pavel,

I saw with the help of the following:
e2e.ti.com/.../940136
That I need to set the following registers (LVCMOS mode):
MLBP_SIG_IO_CTRL
MLBP_DAT_IO_CTRL

Now it all works.
Thank you very much!
Ran

0 Pavel Botev over 10 years ago in reply to Pavel Botev

TI__Guru**** 170625 points

Ran,

Is this issue resolved? I see you have verified the linux forum thread below:
e2e.ti.com/.../437181

BR
Pavel

0 ranchu over 10 years ago in reply to Pavel Botev

Guru 20755 points

Hi Pavel,

Yes it's solved.
Thank you very much!
It is related to LVCMOD in registers
MLBP_SIG_IO_CTRL
MLBP_DAT_IO_CTRL

Thank you all very much!
Ran

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GPIO interrupt - problem with kernel APIs