In the HW_UPP.H file in starterware, the following #defines are found:
#define UPP_UPPID (0x0)
#define UPP_UPPCR (0x4)
#define UPP_UPDLB (0x8)
#define UPP_UPCTL (0x10)
#define UPP_UPICR (0x14)
#define UPP_UPIVR (0x18)
#define UPP_UPTCR (0x1C)
#define UPP_UPISR (0x20)
#define UPP_UPIER (0x24)
#define UPP_UPIES (0x2C)
#define UPP_UPIEC (0x30)
#define UPP_UPEOI (0x40)
#define UPP_UPID0 (0x44)
#define UPP_UPID1 (0x48)
#define UPP_UPID2 (0x50)
#define UPP_UPIS0 (0x54)
#define UPP_UPIS1 (0x58)
#define UPP_UPIS2 (0x60)
#define UPP_UPQD0 (0x64)
#define UPP_UPQD1 (0x68)
#define UPP_UPQD2 (0x6C)
#define UPP_UPQS0 (0x70)
#define UPP_UPQS1 (0x74)
#define UPP_UPQS2 (0x78)
In the C6748 tech ref, the following is found:
0 UPPID uPP Peripheral Identification Register Section 29.3.1
4h UPPCR uPP Peripheral Control Register Section 29.3.2
8h UPDLB uPP Digital Loopback Register Section 29.3.3
10h UPCTL uPP Channel Control Register Section 29.3.4
14h UPICR uPP Interface Configuration Register Section 29.3.5
18h UPIVR uPP Interface Idle Value Register Section 29.3.6
1Ch UPTCR uPP Threshold Configuration Register Section 29.3.7
20h UPISR uPP Interrupt Raw Status Register Section 29.3.8
24h UPIER uPP Interrupt Enabled Status Register Section 29.3.9
28h UPIES uPP Interrupt Enable Set Register Section 29.3.10
2Ch UPIEC uPP Interrupt Enable Clear Register Section 29.3.11
30h UPEOI uPP End-of-Interrupt Register Section 29.3.12
40h UPID0 uPP DMA Channel I Descriptor 0 Register Section 29.3.13
44h UPID1 uPP DMA Channel I Descriptor 1 Register Section 29.3.14
48h UPID2 uPP DMA Channel I Descriptor 2 Register Section 29.3.15
50h UPIS0 uPP DMA Channel I Status 0 Register Section 29.3.16
54h UPIS1 uPP DMA Channel I Status 1 Register Section 29.3.17
58h UPIS2 uPP DMA Channel I Status 2 Register Section 29.3.18
60h UPQD0 uPP DMA Channel Q Descriptor 0 Register Section 29.3.19
64h UPQD1 uPP DMA Channel Q Descriptor 1 Register Section 29.3.20
68h UPQD2 uPP DMA Channel Q Descriptor 2 Register Section 29.3.21
70h UPQS0 uPP DMA Channel Q Status 0 Register Section 29.3.22
74h UPQS1 uPP DMA Channel Q Status 1 Register Section 29.3.23
78h UPQS2 uPP DMA Channel Q Status 2 Register Section 29.3.24
You can see that the addresses in RED do not agree with those in the tech ref, data sheet, etc. I am guessing that the documentation is correct and that the starterware has an error? Especially since no driver was written, so this header file was probably not tested?
Anyhow, can you please confirm which is correct. Hard enough getting the thing working right anyhow.
