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AM335 i2c EEPROM

sram
Intellectual 680 points

Hi All,

This is a question about the AM335x I2C starterware code which reads the EEPROM.

I am able to read EEPROM in both interrupt and polling mode and it works fine.

The i2c0 EEPROM address (7 bit slave address is set to 0x50) in my code. But i'm not able to figure out where the READ/WRITE bit

is sent to i2c device. The code which sends the EEPROM address goes like this

/* Data Count specifies the number of bytes to be transmitted */
I2CSetDataCount(SOC_I2C_0_REGS, 0x02); //This is i2C EEPROM memory address

/* Configure I2C controller in Master Transmitter mode */

I2CMasterControl(SOC_I2C_0_REGS, I2C_CFG_MST_TX);

/* Transmit interrupt is enabled */
I2CMasterIntEnableEx(SOC_I2C_0_REGS, I2C_INT_TRANSMIT_READY);

/* Generate Start Condition over I2C bus */
I2CMasterStart(SOC_I2C_0_REGS);

So this code will send i2c Packet as follows

Start bit  7 Bit Slave Addres  Read/Write Bit  EEPROM address MSB   EEPROM LSB....

I wonder how the Read/Write Bit is sent as per the above Code. I'm not able to figure out. Please suggest?

Regards,

  • 0
    TI__Mastermind 30365 points

    sram,

    I believe the R/W bit comes from the slave address that you use.

    0x50: 0101 0000 (Read)

    0x51: 0101 0001 (Write)

    Pg 4479 of the TRM has a paragraph at the end that discusses the addressing. I will also check with a colleague if this is correct, and post back here if I need to correct myself. Hope this helps.

    Lali

  • 0 in reply to Lalindra Jayatilleke
    Intellectual 695 points
    Hello lalindra,
    I assume that the answer given by you may be wrong due to the I2C protocol specification, for Read the Last bit is '1' and write Last bit is '0'.

    Sram:
    The I2C Controller has an intelligence to take care at the bus level depending on the programming sequence.

    I2CMasterControl(SOC_I2C_0_REGS, I2C_CFG_MST_TX);

    From the above statement you are programming to the I2C sub system registers. The Parameter is I2C_CFG_MST_TX , so master is in the transmitter mode, so the controller will know that it is in write mode.


    I2CMasterStart(SOC_I2C_0_REGS);

    After this the controller will start the I2C bus operation in write mode(7 bit slave address and write bit '0') .


    Thanks & Regards
    Rama Krishna
  • 0 in reply to rama krishna
    Intellectual 680 points
    Hi Ramakrishna,

    Thanks for the Reply. It makes sense.

    I2C devices use either 7 bit or 10 bit slave address and hence I2CMasterSlaveAddrSet() function uses the first 7 bits of the 0x50 to set slave address. But in this case, assuming that the last bit of the slave address is used (1 for Read and 0 for Write), first question is how it is used? as we only use 7 bits to set slave address and where the last bit is set for Read/Write?. I tried both i2c_read and i2c_write using the same slave Address 0x50 and it works fine!.

    So your answer that the i2c Controller has intelligence to automatically take care of Read/Write holds good.

    Thanks

    regards,
  • 0 in reply to rama krishna
    TI__Mastermind 30365 points

    Rama/Sram,

    I stand corrected. Thank you for contributing to the discussion and correcting my response.

    Lali