I am trying to set up a DSP/BIOS application with rCSL (not using the DSP/BIOS driver with GIO) and am having trouble with the receive interrupts. My configuration code, which is called from the main function before BIOS initialization is included below (McifConfigureUART). I do the event and interrupt vector mapping in the task function MainMcifTsk for now in case the HWI_ functions assume BIOS is running (doesn't look like they are when I trace through the instructions in the disassembler).
When this runs, the initialization completes, and I can see 'T' character loaded into THR received on the console of a PC attached to UART2. When I send a character back from that terminal, I never get to the ISR (should be getting line status and/or receive data ready), but I can force a read from RBR and get the correct character. I've confirmed the following at runtime:
1) Both receiver interrupts are enabled in the UART IER
2) The GIE bit in CSR is set
3) The appropriate bit is set to enable HWI_9 in the core IER
4) Event 69 for UART2 is mapped to interrupt 9 in the corresponding INTMUX register field
5) The flag for event 69 is being set in the event flags register (bit 5 of EVTSET2)
6) No bits are set in the core IFR for interrupt 9 or any other interrupt.
7) The interrupt pending bit in the UART IIR indicates there is no interrupt pending (0 = interrupt pending according to the uart users guide).
Any thoughts on what I might be missing?
Thanks in advance!
David
PS. This is the only task that runs and the only init function called by main right now.
void MainMcifTsk () {
HWI_Attrs hat = HWI_ATTRS;
Fxn isrfunc = &McifIsr;
HWI_enable();
HWI_eventMap(9,69); //map event to interrupt
HWI_dispatchPlug(9,isrfunc,-1,&hat); //use int4, call isrfunc (McifIsr), CPU transfer - 6x0x needs DMA to write int RAM, default attrs
C64_enableIER(C64_EINT9);
while (1) {
TSK_sleep(100);
}
return;
}
Int McifIsr() {
char inp;
CSL_UartRegsOvly uartRegs = (CSL_UartRegsOvly)CSL_UART_2_REGS;;
inp = uartRegs->RBR;
return 0;
}
void McifConfigureUART() {
//Get structure for access to SysCfg registers (pinmux specifically)
CSL_SyscfgRegsOvly syscfgRegs;
//Initialize vars for pinmux values
Uint32 savePinmux0 = 0;
Uint32 savePinmux4 = 0;
//Initialize var for UartRegs
//Uint32 saveUartReg = 0;
//Initialize structure for HWI attributes
//HWI_Attrs hat = HWI_ATTRS;
//Fxn isrfunc = &McifIsr;
/*
//Power up the module - GEL file is handling this for now...
CSL_PscRegsOvly psc0Regs = (CSL_PscRegsOvly)CSL_PSC_0_REGS;
// deassert UART local PSC reset and set NEXT state to ENABLE
psc0Regs->MDCTL[CSL_PSC_UART0] = CSL_FMKT( PSC_MDCTL_NEXT, ENABLE )
| CSL_FMKT( PSC_MDCTL_LRST, DEASSERT );
// move UART PSC to Next state
psc0Regs->PTCMD = CSL_FMKT( PSC_PTCMD_GO0, SET );
// wait for transition
while ( CSL_FEXT( psc0Regs->MDSTAT[CSL_PSC_UART0], PSC_MDSTAT_STATE )
!= CSL_PSC_MDSTAT_STATE_ENABLE );
*/
//Unlock BOOTCFG module before pinmux configuration
KICK0 = KICK0_UNLOCK_CODE;
KICK1 = KICK1_UNLOCK_CODE;
syscfgRegs = (CSL_SyscfgRegsOvly)CSL_SYSCFG_0_REGS;
//Set the pinmux registers to enable UART2 (exposed on EVM connector)
savePinmux0 = (syscfgRegs->PINMUX0 &
~(CSL_SYSCFG_PINMUX0_PINMUX0_31_28_MASK |
CSL_SYSCFG_PINMUX0_PINMUX0_27_24_MASK));
syscfgRegs->PINMUX0 = (PINMUX3_UART2_ENABLE_PINMUX0 | savePinmux0);
savePinmux4 = (syscfgRegs->PINMUX4 &
~(CSL_SYSCFG_PINMUX4_PINMUX4_23_20_MASK |
CSL_SYSCFG_PINMUX4_PINMUX4_19_16_MASK));
syscfgRegs->PINMUX4 = (PINMUX3_UART2_ENABLE_PINMUX4 | savePinmux4);
uartRegs = (CSL_UartRegsOvly)CSL_UART_2_REGS;
//set baud rate (DLL, DLH)
uartRegs->DLH = 0x00; //"borrowed" from params after bios driver init in demo app
uartRegs->DLL = 0x51; //should give 115,200
//set fifo trigger level (probably want to get every char...)
//first set FIFOEN in FCR, then write remaining values
//uartRegs->FCR = (CSL_UART_FCR_FIFOEN_ENABLE << CSL_UART_FCR_FIFOEN_SHIFT);
//uartRegs->FCR = (CSL_UART_FCR_RXFIFTL_CHAR1 << CSL_UART_FCR_RXFIFTL_SHIFT) |
// (CSL_UART_FCR_DMAMODE1_DISABLE << CSL_UART_FCR_DMAMODE1_SHIFT) |
// (CSL_UART_FCR_FIFOEN_ENABLE << CSL_UART_FCR_FIFOEN_SHIFT);
//Write protocol settings to LCR
uartRegs->LCR = (CSL_UART_LCR_RESETVAL) |
(CSL_UART_LCR_WLS_8BITS << CSL_UART_LCR_WLS_SHIFT);
//Write MCR to configure flow control (uC not doing flow control so skip this)
//Write PWREMU_MGMT setting UTRST, URRST to enable and set the free bit so that UART will keep running after emu halt
//saveUartReg = uartRegs->PWREMU_MGMT & ~CSL_UART_PWREMU_MGMT_FREE_MASK; //clear the bit
//saveUartReg |= (CSL_UART_PWREMU_MGMT_FREE_RUN << CSL_UART_PWREMU_MGMT_FREE_SHIFT); //set/clear as requested
uartRegs->PWREMU_MGMT = (CSL_UART_PWREMU_MGMT_RESETVAL) |
(CSL_UART_PWREMU_MGMT_UTRST_ENABLE << CSL_UART_PWREMU_MGMT_UTRST_SHIFT) |
(CSL_UART_PWREMU_MGMT_URRST_ENABLE << CSL_UART_PWREMU_MGMT_URRST_SHIFT) |
(CSL_UART_PWREMU_MGMT_FREE_RUN << CSL_UART_PWREMU_MGMT_FREE_SHIFT);
//Enable receive data available interrupt
uartRegs->IER = (CSL_UART_IER_RESETVAL) |
(CSL_UART_IER_ERBI_ENABLE << CSL_UART_IER_ERBI_SHIFT) |
(CSL_UART_IER_ELSI_ENABLE << CSL_UART_IER_ELSI_SHIFT);
//Setup the interrupt
//hat default values are okay (might want to change masking or args later)
//See SPRUGM7C, page 33 for event ids
//UART0 - event 38
//UART1 - event 46
//UART2 - event 69
//Moved this to task function after DSP/BIOS init to see if that's the problem (and tried an interrupt not connected to the ECM)
//HWI_eventMap(4,69); //map event to interrupt
//HWI_dispatchPlug(4,isrfunc,-1,&hat); //use int4, call isrfunc (McifIsr), CPU transfer - 6x0x needs DMA to write int RAM, default attrs
//C64_enableIER(C64_EINT4);
uartRegs->THR = 'T';
}
DSP BIOS .tcf:
utils.loadPlatform("ti.platforms.evm6748");
/* The following DSP/BIOS Features are enabled. */
bios.enableRealTimeAnalysis(prog);
bios.enableRtdx(prog);
bios.enableTskManager(prog);
bios.TSK.instance("TSK_idle").order = 1;
bios.MEM.USERCOMMANDFILE = 0;
bios.MEM.STACKSIZE = 0x10000;
bios.TSK.create("McifTsk");
bios.TSK.instance("McifTsk").order = 2;
bios.TSK.instance("McifTsk").fxn = prog.extern("MainMcifTsk");
bios.GBL.C64PLUSMAR128to159 = 0x0000ffff;
bios.MEM.BIOSSEG = prog.get("DDR");
bios.MEM.SYSINITSEG = prog.get("DDR");
bios.MEM.TEXTSEG = prog.get("DDR");
bios.MEM.HWISEG = prog.get("DDR");
bios.MEM.HWIVECSEG = prog.get("DDR");
bios.MEM.RTDXTEXTSEG = prog.get("DDR");
bios.LOG.create("DVTEvent_Log");
bios.LOG.instance("DVTEvent_Log").bufLen = 8192;
bios.LOG.create("trace");
bios.LOG.instance("trace").bufLen = 1024;
bios.TSK.instance("McifTsk").stackSize = 16384;
bios.MEM.NOMEMORYHEAPS = 0;
bios.MEM.instance("DDR").createHeap = 1;
bios.MEM.BIOSOBJSEG = prog.get("DDR");
bios.MEM.MALLOCSEG = prog.get("DDR");
bios.PWRM.ENABLE = 0;
// !GRAPHICAL_CONFIG_TOOL_SCRIPT_INSERT_POINT!
prog.gen();
