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EMIF controller and buffering for Keystone II

Other Parts Discussed in Thread: TCI6638K2K

I am using a Keystone II (TCI6638K2K) processor and am putting 2 different devices on the EMIF bus (CS0 and CS2). On CS0 I have nand flash and it is running in Nand mode. On CS2 I have a bus that only uses the EMIF Data Pins (don't care about addressing) and WE pins as a strobe. On the CS2 bus I would like to write out 16-bit words on the data bus 1 after another. In order to do that I need to know a little more about how the controller uses the memory mapped IO section of memory for transfers.

Can I continuously write 16-bit words to a single address in memory? If I do that, will the EMIF controller buffer the words I write to the IO memory since the cpu can write to that section of memory much faster than the EMIF bus can handle? If not, is there a way to tell when the EMIF controller is finished writing to the bus and that I can write my next word to IO memory?

Would it be better to just write to consecutive addresses so that the EMIF controller writes them out consecutively? Even if I do that, how do I know when the EMIF bus is done writing the words that I have written to the memory mapped section?

  • Hi Bill,
    Moved this thread over device forum for faster response. Thank you for your patience.
  • Hello Bill,

    A. For back to back 16 bit word writes.
    As long as all 16bits of data pins from K2K are hooked to the I/O pins of device on CS2, then the consecutive writes should achieve this. The WE pin can be used to get only the data phase of each of these writes, so the address and command phases can be ignored by the device on CS2.
    ASIZE field in A2CR register defines data bus size.
    Writes to address range 0x00 3800 0000 to 0x00 3BFF FFFF will be sent out to EMIF16 CE2 (CS2) space.
    Two bits from the EMIFA bus can be used to distinguish between command/data/address phase.
    So based on the address you write to it will issue either a command/data/address phase.
    Please see 3.1 NAND Flash Mode in EMIF user's guide.


    B. Status Check:
    The WAIT bit in NANDFSR register can be used to check the status of writes (or reads).
    Please check section 3.6 Checking the Status of Operation in EMIF guide.


    In general since address bus is not used at all for CS2 device the address should not matter as the device would be selected for CS2 transactions. Issuing data phase by writing to required address range is what should do it.


    Please let me know if you have more questions.

    Reference:
    EMIF user's guide: www.ti.com/.../sprugz3


    Thank you,
    Vaibhav