Errors in the EDMA-Interrupt Boot example

Viktor Grytsenko

Hello all,

The program EDMA-Interrupt Boot from
mcsdk_2_01_02_06\tools\boot_loader\examples\pcie\
after commands
sudo rmmod pciedemo.ko
sudo insmod pciedemo.ko
sometimes gives correct result:
.................
Read DMA from DSP ...
DMA test passed!

But sometimes
(about 50% of all starts)
this program gives another result:
..................
Read DMA from DSP ...
DMA test failed with 4 locations !

What is the cause of these errors?
What necassary to do to avoid errors?

I used:
Code Composer Studio 5.2.1.00018
mcsdk_2_01_02_06
MDSEVM6678L/MDXEVMPCI board

TMDSEVM6678L Rev.3B

PCIe adaptor card, labeled with
PCB REV: 17-00107-03; PCA REV: 18-00107-03

OS - Debian7, Ubuntu10.04

Best regards,

over 10 years ago

0 Ganapathi Dhandapani95 over 10 years ago

TI__Mastermind 28085 points

Hi,

Have you modified the the TI example code?

Have you enable the LOCAL_RESET macro on your code? The LOCAL_RESET code part is help for run the pciedemo example at multiple iteration.

Are you facing the same issue on both OS?

Thanks,

0 Viktor Grytsenko over 10 years ago in reply to Ganapathi Dhandapani95

Expert 1225 points

Hi,

Thank you for the quick reply.

>Have you modified the the TI example code?

No.

I used original exampe.

>Have you enable the LOCAL_RESET macro on your code?

/* Must select the endianess */
#define BIG_ENDIAN 0

/* Must select which demo to run */
#define HELLO_WORLD_DEMO 0
#define POST_DEMO 0
#define EDMA_INTC_DEMO 1
#define LOCAL_RESET 1

/* Must select a platform */
#define EVMC6678L 1
#define EVMC6670L 0
#define EVMC6657L 0

>The LOCAL_RESET code part is help for run the pciedemo example at multiple iteration.

Yes, I repeaded commands

rmmod pciedemp.ko

insmod pciedemo.ko

many times.

>Are you facing the same issue on both OS?

Yes.

Please look on the *log in the attachment.

Both messages was obtaned after loading the Linux and the first start of the command insmod pciedemo.ko

Regards,

Viktor

---------------------------------------------

P.S.

One updating: I use now

Debian Kwheezy and

Ubuntu14.04 (not Ubuntu10.04 as I wrote earlier)

Fullscreen dmesg_Debian_Kwheezy.log Download

[  118.480197] Finding the device....
[  118.480229] Found TI device
[  118.480233] TI device: vendor=0x104c, dev=0xb005, irq=0x0000000c
[  118.480236] Reading the BAR areas....
[  118.483625] Enabling the device....
[  118.483660] Access PCIE application register ....
[  118.483665] Registering the irq 12 ...
[  118.483689] Allocating consistent memory ...
[  118.500277] Boot entry address is 0x  82e2c0
[  118.501238] Total 5 sections, 0xf30c bytes of data were written
[  120.550234] Write DMA to DSP ...
[  120.562398] Generating interrupt to DSP ...
[  120.687359] Interrupt 12 received from DSP
[  120.687362] Read DMA from DSP ...
[  120.688001] DMA test failed with 4 locations !
[  121.575106] DMA write throughput is: 328.97 MB/s
[  121.575110] DMA read throughput is: 342.55 MB/s
[  121.575113] Freeing consistent memory ...
[  131.498090] Start local reset assert for core (module id): 15 ...
[  131.498096] Start local reset assert for core (module id): 16 ...
[  131.498102] Start local reset assert for core (module id): 17 ...
[  131.498108] Start local reset assert for core (module id): 18 ...
[  131.498113] Start local reset assert for core (module id): 19 ...
[  131.498119] Start local reset assert for core (module id): 20 ...
[  131.498124] Start local reset assert for core (module id): 21 ...
[  131.498130] Start local reset assert for core (module id): 22 ...
[  131.505137] Boot entry address is 0x  878000
[  131.505167] Total 3 sections, 0x748 bytes of data were written
[  131.506161] Boot entry address is 0x  878000
[  131.506191] Total 3 sections, 0x748 bytes of data were written
[  131.507184] Boot entry address is 0x  878000
[  131.507214] Total 3 sections, 0x748 bytes of data were written
[  131.508212] Boot entry address is 0x  878000
[  131.508243] Total 3 sections, 0x748 bytes of data were written
[  131.509236] Boot entry address is 0x  878000
[  131.509266] Total 3 sections, 0x748 bytes of data were written
[  131.510260] Boot entry address is 0x  878000
[  131.510290] Total 3 sections, 0x748 bytes of data were written
[  131.511284] Boot entry address is 0x  878000
[  131.511314] Total 3 sections, 0x748 bytes of data were written
[  131.512312] Boot entry address is 0x  878000
[  131.512342] Total 3 sections, 0x748 bytes of data were written
[  131.530247] MD stat for pid 2 mid 9 state: 3 timeout
[  131.533245] Start local reset de-assert for core (module id): 15 ...
[  131.533251] Start local reset de-assert for core (module id): 16 ...
[  131.533257] Start local reset de-assert for core (module id): 17 ...
[  131.533262] Start local reset de-assert for core (module id): 18 ...
[  131.533268] Start local reset de-assert for core (module id): 19 ...
[  131.533273] Start local reset de-assert for core (module id): 20 ...
[  131.533279] Start local reset de-assert for core (module id): 21 ...
[  131.533285] Start local reset de-assert for core (module id): 22 ...

Fullscreen dmesg_Ubuntu14_04.log Download

[  809.462658] Finding the device....
[  809.462679] Found TI device
[  809.462684] TI device: vendor=0x104c, dev=0xb005, irq=0x0000000c
[  809.462687] Reading the BAR areas....
[  809.464805] Enabling the device....
[  809.465002] Access PCIE application register ....
[  809.465010] Registering the irq 12 ...
[  809.465032] Allocating consistent memory ...
[  809.483107] Boot entry address is 0x  82e2c0
[  809.484173] Total 5 sections, 0xf30c bytes of data were written
[  811.533115] Write DMA to DSP ...
[  811.545277] Generating interrupt to DSP ...
[  811.670238] Interrupt 12 received from DSP
[  811.670241] Read DMA from DSP ...
[  811.672001] DMA test failed with 4 locations !
[  812.556914] DMA write throughput is: 329.05 MB/s
[  812.556919] DMA read throughput is: 342.58 MB/s
[  812.556921] Freeing consistent memory ...
[  822.479134] Start local reset assert for core (module id): 15 ...
[  822.479143] Start local reset assert for core (module id): 16 ...
[  822.479150] Start local reset assert for core (module id): 17 ...
[  822.479157] Start local reset assert for core (module id): 18 ...
[  822.479163] Start local reset assert for core (module id): 19 ...
[  822.479169] Start local reset assert for core (module id): 20 ...
[  822.479176] Start local reset assert for core (module id): 21 ...
[  822.479182] Start local reset assert for core (module id): 22 ...
[  822.486192] Boot entry address is 0x  878000
[  822.486229] Total 3 sections, 0x748 bytes of data were written
[  822.487224] Boot entry address is 0x  878000
[  822.487258] Total 3 sections, 0x748 bytes of data were written
[  822.488257] Boot entry address is 0x  878000
[  822.488292] Total 3 sections, 0x748 bytes of data were written
[  822.489287] Boot entry address is 0x  878000
[  822.489321] Total 3 sections, 0x748 bytes of data were written
[  822.490315] Boot entry address is 0x  878000
[  822.490349] Total 3 sections, 0x748 bytes of data were written
[  822.491344] Boot entry address is 0x  878000
[  822.491377] Total 3 sections, 0x748 bytes of data were written
[  822.492377] Boot entry address is 0x  878000
[  822.492412] Total 3 sections, 0x748 bytes of data were written
[  822.493407] Boot entry address is 0x  878000
[  822.493440] Total 3 sections, 0x748 bytes of data were written
[  822.511350] MD stat for pid 2 mid 9 state: 3 timeout
[  822.514351] Start local reset de-assert for core (module id): 15 ...
[  822.514358] Start local reset de-assert for core (module id): 16 ...
[  822.514364] Start local reset de-assert for core (module id): 17 ...
[  822.514371] Start local reset de-assert for core (module id): 18 ...
[  822.514377] Start local reset de-assert for core (module id): 19 ...
[  822.514383] Start local reset de-assert for core (module id): 20 ...
[  822.514390] Start local reset de-assert for core (module id): 21 ...
[  822.514396] Start local reset de-assert for core (module id): 22 ...

0 Ganapathi Dhandapani95 over 10 years ago in reply to Viktor Grytsenko

TI__Mastermind 28085 points

Hi,

TI has tested this example on a Ubuntu 10.04 and 12.04(32 and 64 bit). It is works fine for multiple iterations.

Have you using Ubuntu14.04 (64-bit) OS for your testing? DSP reset command is not properly working on Ubuntu14.04 (64-bit) OS. Take a look at below link:
e2e.ti.com/.../1483384

Thanks,

0 Viktor Grytsenko over 10 years ago in reply to Ganapathi Dhandapani95

Expert 1225 points

Hi,

please look on the new *.log files in the attachment.

These *.log was obtained in the Ubuntu10.04 and Ubuntu12.04

These results was obtained after loading the OS Ubuntu and the first start of the command insmod pciedemo.ko

To get failed result after first start I had to reload OS some times.

The local reset command could not to inpact on this result,

because of the local reset had place after the message:

"DMA test failed with 4 locations !"

Can I ask you to inspect the messages from EDMA example after about 20 starts of the commands:

rmmod pciedemp.ko

insmod pciedemo.ko

Thank you,

Regards,

Viktor.

Fullscreen dmesg_Ubumtu10_04.log Download

[  204.899674] Finding the device....
[  204.899696] Found TI device
[  204.899698] TI device: vendor=0x104c, dev=0xb005, irq=0x0000000c
[  204.899700] Reading the BAR areas....
[  204.901906] Enabling the device....
[  204.901924] pci 0000:01:00.0: PCI INT A -> GSI 16 (level, low) -> IRQ 16
[  204.901931] pci 0000:01:00.0: setting latency timer to 64
[  204.901940] Access PCIE application register ....
[  204.901943] Registering the irq 12 ...
[  204.901963] Allocating consistent memory ...
[  204.917236] Boot entry address is 0x  82e2c0
[  204.918152] Total 5 sections, 0xf30c bytes of data were written
[  206.975913] Write DMA to DSP ...
[  206.988089] Generating interrupt to DSP ...
[  207.113115] Interrupt 12 received from DSP
[  207.113118] Read DMA from DSP ...
[  207.116003] DMA test failed with 4 locations !
[  208.000094] DMA write throughput is: 328.81 MB/s
[  208.000098] DMA read throughput is: 342.37 MB/s
[  208.000101] Freeing consistent memory ...
[  218.078193] Start local reset assert for core (module id): 15 ...
[  218.078200] Start local reset assert for core (module id): 16 ...
[  218.078205] Start local reset assert for core (module id): 17 ...
[  218.078211] Start local reset assert for core (module id): 18 ...
[  218.078216] Start local reset assert for core (module id): 19 ...
[  218.078221] Start local reset assert for core (module id): 20 ...
[  218.078226] Start local reset assert for core (module id): 21 ...
[  218.078231] Start local reset assert for core (module id): 22 ...
[  218.085239] Boot entry address is 0x  878000
[  218.085270] Total 3 sections, 0x748 bytes of data were written
[  218.086263] Boot entry address is 0x  878000
[  218.086293] Total 3 sections, 0x748 bytes of data were written
[  218.087286] Boot entry address is 0x  878000
[  218.087316] Total 3 sections, 0x748 bytes of data were written
[  218.088316] Boot entry address is 0x  878000
[  218.088345] Total 3 sections, 0x748 bytes of data were written
[  218.089339] Boot entry address is 0x  878000
[  218.089369] Total 3 sections, 0x748 bytes of data were written
[  218.090362] Boot entry address is 0x  878000
[  218.090392] Total 3 sections, 0x748 bytes of data were written
[  218.091385] Boot entry address is 0x  878000
[  218.091415] Total 3 sections, 0x748 bytes of data were written
[  218.092414] Boot entry address is 0x  878000
[  218.092444] Total 3 sections, 0x748 bytes of data were written
[  218.110354] MD stat for pid 2 mid 9 state: 3 timeout
[  218.113353] Start local reset de-assert for core (module id): 15 ...
[  218.113358] Start local reset de-assert for core (module id): 16 ...
[  218.113364] Start local reset de-assert for core (module id): 17 ...
[  218.113369] Start local reset de-assert for core (module id): 18 ...
[  218.113374] Start local reset de-assert for core (module id): 19 ...
[  218.113380] Start local reset de-assert for core (module id): 20 ...
[  218.113385] Start local reset de-assert for core (module id): 21 ...
[  218.113390] Start local reset de-assert for core (module id): 22 ...

Fullscreen dmesg_Ubuntu12_04.log Download

[  285.914345] Finding the device....
[  285.914367] Found TI device
[  285.914372] TI device: vendor=0x104c, dev=0xb005, irq=0x0000000c
[  285.914375] Reading the BAR areas....
[  285.916698] Enabling the device....
[  285.916899] Access PCIE application register ....
[  285.916905] Registering the irq 12 ...
[  285.916927] Allocating consistent memory ...
[  285.933736] Boot entry address is 0x  82e2c0
[  285.934658] Total 5 sections, 0xf30c bytes of data were written
[  287.982682] Write DMA to DSP ...
[  287.994839] Generating interrupt to DSP ...
[  288.119746] Interrupt 12 received from DSP
[  288.119752] Read DMA from DSP ...
[  288.123718] DMA test failed with 4 locations !
[  288.986585] DMA write throughput is: 329.24 MB/s
[  288.986590] DMA read throughput is: 342.72 MB/s
[  288.986593] Freeing consistent memory ...
[  298.903974] Start local reset assert for core (module id): 15 ...
[  298.903984] Start local reset assert for core (module id): 16 ...
[  298.903991] Start local reset assert for core (module id): 17 ...
[  298.903998] Start local reset assert for core (module id): 18 ...
[  298.904023] Start local reset assert for core (module id): 19 ...
[  298.904037] Start local reset assert for core (module id): 20 ...
[  298.904044] Start local reset assert for core (module id): 21 ...
[  298.904051] Start local reset assert for core (module id): 22 ...
[  298.911055] Boot entry address is 0x  878000
[  298.911089] Total 3 sections, 0x748 bytes of data were written
[  298.912087] Boot entry address is 0x  878000
[  298.912120] Total 3 sections, 0x748 bytes of data were written
[  298.913115] Boot entry address is 0x  878000
[  298.913146] Total 3 sections, 0x748 bytes of data were written
[  298.914142] Boot entry address is 0x  878000
[  298.914173] Total 3 sections, 0x748 bytes of data were written
[  298.915168] Boot entry address is 0x  878000
[  298.915200] Total 3 sections, 0x748 bytes of data were written
[  298.916198] Boot entry address is 0x  878000
[  298.916231] Total 3 sections, 0x748 bytes of data were written
[  298.917226] Boot entry address is 0x  878000
[  298.917258] Total 3 sections, 0x748 bytes of data were written
[  298.918253] Boot entry address is 0x  878000
[  298.918284] Total 3 sections, 0x748 bytes of data were written
[  298.936188] MD stat for pid 2 mid 9 state: 3 timeout
[  298.939184] Start local reset de-assert for core (module id): 15 ...
[  298.939191] Start local reset de-assert for core (module id): 16 ...
[  298.939198] Start local reset de-assert for core (module id): 17 ...
[  298.939204] Start local reset de-assert for core (module id): 18 ...
[  298.939211] Start local reset de-assert for core (module id): 19 ...
[  298.939217] Start local reset de-assert for core (module id): 20 ...
[  298.939224] Start local reset de-assert for core (module id): 21 ...
[  298.939231] Start local reset de-assert for core (module id): 22 ...

0 Ganapathi Dhandapani95 over 10 years ago in reply to Viktor Grytsenko

TI__Mastermind 28085 points

Hi,

Thanks for your log message. I try to reproduce your issue and get back to you.

Processors

Processors forum

Errors in the EDMA-Interrupt Boot example