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EDMA3 completion interrupt come early, or the data DMA'ed to memory late.

SGQ
Expert 2875 points

Hi,

I am setting EDMA3 to transfer data from McBSP to internal L2 memory.  In some case, When the EDMA3 completion interrupt comes in and last few words are not copied to memory yet.  With a wait of about 800us,  only then all the data gets into the memory.

Is it a known problem?  If it is, when does TI expect to fix it?

Thank you.

Steve

  • 0
    TI__Mastermind 35645 points

    Hi,

    Thanks for your post.

    Is your TR programmed for normal completion or early completion? Did you configured EDMA for chain triggered transfer? Usually the TR packets from EDMA CC would be queued in the TC and would be serviced based on priority mechanism. Please check the TCCMODE bit field of OPT and see Table 2-3 from the below doc:

    http://www.ti.com/lit/ug/sprugs5b/sprugs5b.pdf

    In case, if TR is programmed for early completion, it should be quite normal since the transfer is considered to be complete after the EDMACC submits a TR to the EDMATC but the TC may still be transferring the data and in this mode, the channel controller would generate the TCC internally which indicates the transfer is said to be complete but the actual transfer would be still in progress.

    Alternatively, you could also think of the queue priority mechanism of TC's TR packets as well data traffic and due to which, you could also experience the latency of DMA data transfer to the destination memory.

    With the above, it cannot be a known problem and there may be scenarios which would experience the same issue.

    Thanks & regards,

    Sivaraj K

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  • 0 in reply to Sivaraj Kuppuraj
    Expert 2875 points

    Hi Sivaraj,

    Thanks for the reply.

    My TR is programmed for normal completion, TCCMODE = 0.  My EDMA is configured for chaining, ping pong buffers.

    Could explain the queue priority issue in detail?  Why would that cause the latency of EMDA data transfer?

    Thank you.

    Regards,

    Steve

  • 0 in reply to SGQ
    TI__Mastermind 35645 points

    Hi,

    In my opinion, if you configure EDMA for subsequent chained transfers, this latency is usually common and it would be better to program TR for early completion for chain triggered DMA data transfers which suits the most. Usually in event triggered transfers, the final TCC would enable the IPR bits followed by IER to assert the EDMA completion interrupt but in chain triggered transfers, the TCC would enable the chain triggered interrupt in CER for subsequent transfer through reloading with linked PaRAM Set.

    I believe, latency of DMA data transfer would be common in the case of chain triggered transfers since it would generate the TCC internally which considers the transfer is completed but actual transfer would be still in progress where the actual data DMA'ed to the destination address would still exist.

    Please validate the above info. as well the TC queue priority mechanism based on which the TR packets are queued in FIFO on priority basis.

    http://www.ti.com/lit/ug/sprugs5b/sprugs5b.pdf

    Thanks & regards,

    Sivaraj K

    ------------------------------------------------------------------------------------------------------

    Please click the Verify Answer button on this post if it answers your question.

    -------------------------------------------------------------------------------------------------------

  • 0 in reply to Sivaraj Kuppuraj
    Expert 2875 points

    Hi Sivaraj,

    Thanks for the reply.  I am not quite sure of your suggestion of using early completion for chainned DMA (ping pong in my case).

    I am using normal completion which is already causes the DMA'ed data transfering late.  Using early completion would fix the problem?

    Are you saying that latency of DMA data transfer is a common (known) problem?  If it is, what is suggested work around other than just wait?

    Thank you.

    Steve