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C6472 or C6474 SRIO booting - can the boot host use srio to configure DSP's DDR registers

Eddie3909
Guru 10385 points

Hi

I'd like to use SRIO boot and need the boot host to configure DDR before loading code to it. Is it possible to assess the DDR configuration registers? I've read the SRIO user guides and the boot doc and have not found anything that saying this can't be done, but haven't found anything saying it can be done either.

I'm hoping that a secondary boot loader is not required to configure DDR.

Cheers

  • 0
    TI__Guru* 84110 points

    Yes, the SRIO host can access the DDR memory controller registers.

    For the C6474, the datasheet sprs552 (e) in section 4.1 on page 51 says "For example, the DDR2 memory controller registers are accessed through their data bus interface." Then in Figure  on page 53 shows the RapidIO master connected to the master side of SCR-B and the DDR2 EMIF connected to the slave side. Then Table  on page 54 confirms that the RapidIO master can access the DDR2 peripheral. Not the most obvious way to find an answer.

    I did not find the same statement for the C6472, although I am confident that the SRIO can access the DDR2 memory controller registers. We can get someone else to answer for the C6472.

  • 0 in reply to RandyP
    Guru 10385 points

    Thanks for the info.

    Perhaps the C6472 datasheet sprs612 indicates its possible in table 4.1 p91? It shows the RapidIO being master of DDR. Opps, just realized thats the DMA SCR Connection Matrix.

    What is concerning is the Configuration Switched Central Resource figure 4-3 p93 (sprs612b C6472 datasheet). It does not show the same DDR EMIF connection to the SCR as shown in the C6474 datasheet sprs552e Fig 4-1 p53 (as you pointed me to earlier). Granted, I may be comparing apples to oranges since the C6472 figure is a configuration SCR.

    Hope you are right.

    Cheers

  • 0 in reply to Eddie3909
    TI__Mastermind 30825 points

    Eddie,

    The equivalent to the Fig 4-1 of C6472, would be Fig 4-1 on C6474.  These are the Data SCR bridges. 

    Fig 4-3 of C6472 datasheet (it's counterpart is Fig 4-2 of C6474 datasheet) which is the config portion only which is connected to the data side over the Config SCR (listed as SCRD(CFG) on C6474's Fig 4-1 and CFG SCR on C6472.) 

    That said Randy is correct in that both C6472 and C6474 both can master the DDR and SRIO has access to the Memory Mapped Registers of the DDR2 Configuration Registers and can program them in order to configure the DDR2 Inteface.

    Best Regards,

    Chad

  • 0 in reply to Chad Courtney
    Guru 10385 points

    Thanks Randy and Chad

    Chad Courtney said:
    The equivalent to the Fig 4-1 of C6472, would be Fig 4-1 on C6474.  These are the Data SCR bridges. 

    This is what confused me. The C6472 Fig 4-1 p90 (sprs612b) is titled "DMA Switched Central Resource" which as a novice meant to me that it was not the same as a plain Jane "Switched Central Resource" in C6474 Fig 4-1 p53 (sprs552e). I thought they were different SCRs because of the DMA naming.

    Chad Courtney said:
    Fig 4-3 of C6472 datasheet (it's counterpart is Fig 4-2 of C6474 datasheet) which is the config portion only which is connected to the data side over the Config SCR (listed as SCRD(CFG) on C6474's Fig 4-1 and CFG SCR on C6472.) 

    That REALLY helps in understanding the bus. Thanks a bunch.

    Cheers