C6472/C6474 Power Sleep Controller - waking up the chip

Eddie said:

In the documents figure "Power and Clock Domains", what is LL2?

I found one place in the C6472 datasheet where you might be able to guess what LL2 means, because in Table 2-1 it talks about SL2 being shared memory. This is not good enough, though. We should define these acronyms in every document where they are used, including the datasheet and the PSC User's Guide.

LL2 is Local Level 2 memory. SL2 is Shared Level 2 memory. We should make that more clear.

Eddie said:

I've read sprueg3b.pdf and it says each core (megamodule) can be clock gated using the LPSC. If I want to power down, I use the GPSC. If I gate the clock using the LPSC and all Megamodules go to IDLE, what is the mechanism for reprogramming the LPSC to ungate the clocks?

The PSC is very cleverly designed to give you a lot of flexibility in power management. But there are practical limitations. Please re-read the PSC User's Guide Section 4.1 C64x+ Megamodule Clock Gating to understand the requirements and limitations for clock gating the Megamodules.

Hi

Thanks for the info.

Does the statement in 4.1 "at least one C64x+ Megamodule should be alive to enable the clock to other C64x+ Megamodules" preclude the use of an external interrupt or HPI to enable the clock to a megamodule? I suppose it does for the interrupt case since the core needs a clock to run code after the interrupt occurs.

The HPI does not have access to the LPSC registers? (at least that is what I see from sprs612b (C6472 datasheet) Table 4-1 p 91.)

If I follow the HPI and SRIO input from Fig 4-1 "DMA Switched Central Resource" p90 (sprs612b), it can access the CFG SCR, which in turn can access the PSC on Fig 4-3 "Configuration Switched Central Resource" p93. This would mean that both can be used to program the LPSC or GPSC for clock gating and power down of all cores. True?

Cheers