Is there an example dts file for custom hardware both NAND and another memory device are connected to GPMC interface?

yang yang2

Other Parts Discussed in Thread: AM3352

Hi, there

Our custom hardware is almost functional compliant with AM3352_EVM. Except that FPGA instead of LCD is connected to GPMC interface. I had searched the threads other one posted. In the thread it said that another GPMC node can be added. But my question is that the NAND GPMC node is already existed. What should I do to add another node?

Best Regards

Yang

over 10 years ago

0 Biser Gatchev-XID over 10 years ago

TI__Guru**** 393215 points

Hi,

I will forward this to the SW team.

0 Yordan Kovachev over 10 years ago

TI__Guru**** 161600 points

Hi Yang,

If I understand your question correctly, you would like an example GPMC node that does not have a NAND child node, but another child node, which is appropriate for connecting the interface with FPGA, right?

If so, can you try the following :

Fullscreen 8171.gpmc.txt Download

	gpmc_pins: pinmux_gpmc_pins {
		pinctrl-single,pins = <
			0x000 0x30	/* gpmc_ad0.gpmc_ad0 MODE0 | INPUT | PULLUP */
			0x004 0x30	/* gpmc_ad1.gpmc_ad1 MODE0 | INPUT | PULLUP */
			0x008 0x30	/* gpmc_ad2.gpmc_ad2 MODE0 | INPUT | PULLUP */
			0x00C 0x30	/* gpmc_ad3.gpmc_ad3 MODE0 | INPUT | PULLUP */
			0x010 0x30	/* gpmc_ad4.gpmc_ad4 MODE0 | INPUT | PULLUP */
			0x014 0x30	/* gpmc_ad5.gpmc_ad5 MODE0 | INPUT | PULLUP */
			0x018 0x30	/* gpmc_ad6.gpmc_ad6 MODE0 | INPUT | PULLUP */
			0x01C 0x30	/* gpmc_ad7.gpmc_ad7 MODE0 | INPUT | PULLUP */
			0x020 0x30	/* gpmc_ad8.gpmc_ad8 MODE0 | INPUT | PULLUP */
			0x024 0x30	/* gpmc_ad9.gpmc_ad9 MODE0 | INPUT | PULLUP */
			0x028 0x30	/* gpmc_ad10.gpmc_ad10 MODE0 | INPUT | PULLUP */
			0x02C 0x30	/* gpmc_ad11.gpmc_ad11 MODE0 | INPUT | PULLUP */
			0x030 0x30	/* gpmc_ad12.gpmc_ad12 MODE0 | INPUT | PULLUP */
			0x034 0x30	/* gpmc_ad13.gpmc_ad13 MODE0 | INPUT | PULLUP */
			0x038 0x30	/* gpmc_ad14.gpmc_ad14 MODE0 | INPUT | PULLUP */
			0x03C 0x30	/* gpmc_ad15.gpmc_ad15 MODE0 | INPUT | PULLUP */
			0x080 0x08	/* gpmc_cscn1.gpmc_cscn1 MODE0 | OUTPUT */
			0x084 0x08	/* gpmc_cscn2.gpmc_cscn2 MODE0 | OUTPUT */
			0x08C 0x28	/* gpmc_clk.gpmc_clk MODE0 | OUTPUT */
			0x090 0x08	/* gpmc_advn_ale.gpmc_advn_ale MODE0 | OUTPUT */
			0x094 0x08	/* gpmc_oen_ren.gpmc_oen_ren MODE0 | OUTPUT */
			0x098 0x08	/* gpmc_wen.gpmc_wen MODE0 | OUTPUT */

			0x070 0x30	/* gpmc_wait0.gpmc_wait0 MODE0 | INPUT | PULLUP */

		>;
	};


&gpmc {
			status = "okay";
			pinctrl-names = "default";
			pinctrl-0 = <&gpmc_pins>;

			#address-cells = <2>;
			#size-cells = <1>;

			/* chip select ranges */
			ranges = <1 0 0x01000000 0x1000000>;

			ethernet{
						reg = <1 0 0x01000000>;	/*CSn1*/
				
				bank-width = <2>;		/* GPMC_CONFIG1_DEVICESIZE(1) */

				/*gpmc,burst-write;*/
				/*gpmc,burst-read;*/
				/*gpmc,burst-wrap;*/
				gpmc,sync-read;		/* GPMC_CONFIG1_READTYPE_ASYNC */
				gpmc,sync-write;		/* GPMC_CONFIG1_WRITETYPE_ASYNC */
				gpmc,clk-activation-ns = <0>;	/* GPMC_CONFIG1_CLKACTIVATIONTIME(2) */
				gpmc,burst-length = <16>;	/* GPMC_CONFIG1_PAGE_LEN(2) */
				gpmc,mux-add-data = <2>;	/* GPMC_CONFIG1_MUXTYPE(2) */

				gpmc,sync-clk-ps = <20000>;	/* CONFIG2 */

				gpmc,cs-on-ns = <0>;
				gpmc,cs-rd-off-ns = <100>;
				gpmc,cs-wr-off-ns = <40>;

				gpmc,adv-on-ns = <0>;		/* CONFIG3 */
				gpmc,adv-rd-off-ns = <20>;
				gpmc,adv-wr-off-ns = <20>;

				gpmc,we-on-ns = <20>;		/* CONFIG4 */
				gpmc,we-off-ns = <40>;
				gpmc,oe-on-ns = <20>;
				gpmc,oe-off-ns = <100>;

				gpmc,page-burst-access-ns = <20>;	/* CONFIG 5 */
				gpmc,access-ns = <80>;
				gpmc,rd-cycle-ns = <120>;
				gpmc,wr-cycle-ns = <60>;
				gpmc,wr-access-ns = <40>;		/* CONFIG 6 */
				gpmc,wr-data-mux-bus-ns = <20>;

				/*gpmc,bus-turnaround-ns = <40>;*/		/* CONFIG6:3:0 = 4 */
				gpmc,cycle2cycle-samecsen;		/* CONFIG6:7 = 1 */
				gpmc,cycle2cycle-delay-ns = <20>;	/* CONFIG6:11:8 = 4 */

				/* not using dma engine yet, but we can get the channel number here */
				dmas = <&edma 1>;
				dma-names = "cscdma";

		};
};

I've had feedback from customers, that manage to connect FPGA to the gpmc with the settings similar as the above. However please note that gpmc settings/timings will most likely need to be changed to fit your customer's use case.

Hope this helps.

Best Regards,

Yordan

0 yang yang2 over 10 years ago in reply to Yordan Kovachev

Expert 1420 points

Hi, Yordan

Thanks for your quick reply. But I am afraid that you might misunderstand my question. Actually I want an example GPMC node that does have an NAND child node and also another child node which is appropriate for connecting the interface with FPGA.

Best Regards

Yang

0 Yordan Kovachev over 10 years ago in reply to yang yang2

TI__Guru**** 161600 points

Hi Yang,

Then try adding the ethernet { part as a second child node in the GPMC parent (refer to the &gpmc node in am335x-evm.dts).

See Documentation/devicetree/bindings/bus/ti-gpmc.txt:

xample for an AM33xx board:

gpmc: gpmc@50000000 {

compatible = "ti,am3352-gpmc";

ti,hwmods = "gpmc";

reg = <0x50000000 0x2000>;

interrupts = <100>;

gpmc,num-cs = <8>;

gpmc,num-waitpins = <2>;

#address-cells = <2>;

#size-cells = <1>;

ranges = <0 0 0x08000000 0x10000000>; /* CS0 @addr 0x8000000, size 0x10000000 */

/* child nodes go here */

};

Best Regards,

Yordan

0 yang yang2 over 10 years ago in reply to Yordan Kovachev

Expert 1420 points

Hi, Yordan

Do you mean something like below? Do I need to add another "ranges = <1 0 0x8000000 0x10000000>; /* CS1: Ethernet */"?

gpmc_pins: pinmux_gpmc_pins {
pinctrl-single,pins = <
0x000 0x30 /* gpmc_ad0.gpmc_ad0 MODE0 | INPUT | PULLUP */
0x004 0x30 /* gpmc_ad1.gpmc_ad1 MODE0 | INPUT | PULLUP */
0x008 0x30 /* gpmc_ad2.gpmc_ad2 MODE0 | INPUT | PULLUP */
0x00C 0x30 /* gpmc_ad3.gpmc_ad3 MODE0 | INPUT | PULLUP */
0x010 0x30 /* gpmc_ad4.gpmc_ad4 MODE0 | INPUT | PULLUP */
0x014 0x30 /* gpmc_ad5.gpmc_ad5 MODE0 | INPUT | PULLUP */
0x018 0x30 /* gpmc_ad6.gpmc_ad6 MODE0 | INPUT | PULLUP */
0x01C 0x30 /* gpmc_ad7.gpmc_ad7 MODE0 | INPUT | PULLUP */
0x020 0x30 /* gpmc_ad8.gpmc_ad8 MODE0 | INPUT | PULLUP */
0x024 0x30 /* gpmc_ad9.gpmc_ad9 MODE0 | INPUT | PULLUP */
0x028 0x30 /* gpmc_ad10.gpmc_ad10 MODE0 | INPUT | PULLUP */
0x02C 0x30 /* gpmc_ad11.gpmc_ad11 MODE0 | INPUT | PULLUP */
0x030 0x30 /* gpmc_ad12.gpmc_ad12 MODE0 | INPUT | PULLUP */
0x034 0x30 /* gpmc_ad13.gpmc_ad13 MODE0 | INPUT | PULLUP */
0x038 0x30 /* gpmc_ad14.gpmc_ad14 MODE0 | INPUT | PULLUP */
0x03C 0x30 /* gpmc_ad15.gpmc_ad15 MODE0 | INPUT | PULLUP */
0x080 0x08 /* gpmc_cscn1.gpmc_cscn1 MODE0 | OUTPUT */
0x084 0x08 /* gpmc_cscn2.gpmc_cscn2 MODE0 | OUTPUT */
0x08C 0x28 /* gpmc_clk.gpmc_clk MODE0 | OUTPUT */
0x090 0x08 /* gpmc_advn_ale.gpmc_advn_ale MODE0 | OUTPUT */
0x094 0x08 /* gpmc_oen_ren.gpmc_oen_ren MODE0 | OUTPUT */
0x098 0x08 /* gpmc_wen.gpmc_wen MODE0 | OUTPUT */

0x070 0x30 /* gpmc_wait0.gpmc_wait0 MODE0 | INPUT | PULLUP */

>;
};

&gpmc {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&gpmc_pins>;
ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */
nand@0,0 {
reg = <0 0 0>; /* CS0, offset 0 */
ti,nand-ecc-opt = "bch8";
ti,elm-id = <&elm>;
nand-bus-width = <8>;
gpmc,device-width = <1>;
gpmc,sync-clk-ps = <0>;
gpmc,cs-on-ns = <0>;
gpmc,cs-rd-off-ns = <44>;
gpmc,cs-wr-off-ns = <44>;
gpmc,adv-on-ns = <6>;
gpmc,adv-rd-off-ns = <34>;
gpmc,adv-wr-off-ns = <44>;
gpmc,we-on-ns = <0>;
gpmc,we-off-ns = <40>;
gpmc,oe-on-ns = <0>;
gpmc,oe-off-ns = <54>;
gpmc,access-ns = <64>;
gpmc,rd-cycle-ns = <82>;
gpmc,wr-cycle-ns = <82>;
gpmc,wait-on-read = "true";
gpmc,wait-on-write = "true";
gpmc,bus-turnaround-ns = <0>;
gpmc,cycle2cycle-delay-ns = <0>;
gpmc,clk-activation-ns = <0>;
gpmc,wait-monitoring-ns = <0>;
gpmc,wr-access-ns = <40>;
gpmc,wr-data-mux-bus-ns = <0>;
/* MTD partition table */
/* All SPL-* partitions are sized to minimal length
* which can be independently programmable. For
* NAND flash this is equal to size of erase-block */
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "NAND.SPL";
reg = <0x00000000 0x000020000>;
};
partition@1 {
label = "NAND.SPL.backup1";
reg = <0x00020000 0x00020000>;
};
partition@2 {
label = "NAND.SPL.backup2";
reg = <0x00040000 0x00020000>;
};
partition@3 {
label = "NAND.SPL.backup3";
reg = <0x00060000 0x00020000>;
};
partition@4 {
label = "NAND.u-boot-spl-os";
reg = <0x00080000 0x00040000>;
};
partition@5 {
label = "NAND.u-boot";
reg = <0x000C0000 0x00100000>;
};
partition@6 {
label = "NAND.u-boot-env";
reg = <0x001C0000 0x00020000>;
};
partition@7 {
label = "NAND.u-boot-env.backup1";
reg = <0x001E0000 0x00020000>;
};
partition@8 {
label = "NAND.kernel";
reg = <0x00200000 0x00800000>;
};
partition@9 {
label = "NAND.file-system";
reg = <0x00A00000 0x0F600000>;
};
};

ethernet{
reg = <1 0 0x01000000>; /*CSn1*/

bank-width = <2>; /* GPMC_CONFIG1_DEVICESIZE(1) */

/*gpmc,burst-write;*/
/*gpmc,burst-read;*/
/*gpmc,burst-wrap;*/
gpmc,sync-read; /* GPMC_CONFIG1_READTYPE_ASYNC */
gpmc,sync-write; /* GPMC_CONFIG1_WRITETYPE_ASYNC */
gpmc,clk-activation-ns = <0>; /* GPMC_CONFIG1_CLKACTIVATIONTIME(2) */
gpmc,burst-length = <16>; /* GPMC_CONFIG1_PAGE_LEN(2) */
gpmc,mux-add-data = <2>; /* GPMC_CONFIG1_MUXTYPE(2) */

gpmc,sync-clk-ps = <20000>; /* CONFIG2 */

gpmc,cs-on-ns = <0>;
gpmc,cs-rd-off-ns = <100>;
gpmc,cs-wr-off-ns = <40>;

gpmc,adv-on-ns = <0>; /* CONFIG3 */
gpmc,adv-rd-off-ns = <20>;
gpmc,adv-wr-off-ns = <20>;

gpmc,we-on-ns = <20>; /* CONFIG4 */
gpmc,we-off-ns = <40>;
gpmc,oe-on-ns = <20>;
gpmc,oe-off-ns = <100>;

gpmc,page-burst-access-ns = <20>; /* CONFIG 5 */
gpmc,access-ns = <80>;
gpmc,rd-cycle-ns = <120>;
gpmc,wr-cycle-ns = <60>;
gpmc,wr-access-ns = <40>; /* CONFIG 6 */
gpmc,wr-data-mux-bus-ns = <20>;

/*gpmc,bus-turnaround-ns = <40>;*/ /* CONFIG6:3:0 = 4 */
gpmc,cycle2cycle-samecsen; /* CONFIG6:7 = 1 */
gpmc,cycle2cycle-delay-ns = <20>; /* CONFIG6:11:8 = 4 */

/* not using dma engine yet, but we can get the channel number here */
dmas = <&edma 1>;
dma-names = "cscdma";

};
};

Best Regards
Yang

0 yang yang2 over 10 years ago in reply to yang yang2

Expert 1420 points

Hi, Yordan

Is there any update?

0 Yordan Kovachev over 10 years ago in reply to yang yang2

TI__Guru**** 161600 points

Hi Yang,

You should configure the two child nodes to use different chip selects. As I see you use NAND @ CS0 and ethernet @ CS1 (reg = <1 0 0x01000000>; /*CSn1*/), which should be ok.

Best Regards,
Yordan

Processors

Processors forum

Is there an example dts file for custom hardware both NAND and another memory device are connected to GPMC interface?