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EVM6678 DDR WriteBack

msperandio83
Prodigy 20 points

I'm using CCS v5.2.1 with SYS/BIOS  6.33.6.50 MCSDK 2.1.2.5.

I want to share DDR memory area between cores with cache enabled.

I've developed a starting point project with a single .out. I load and run the project on core 0 and core 1.

Both cores read the DDR data.

Both cores modify the read data and shall writeback the data to DDR however Cache_wbInv does not work.

Synchronization between the two cores has been done with an HW Semaphore in order to avoid concurrent access to thw DDR. In the init function permission to read and write to system and user are given.

Please can anyone help me to understand how to write on DDR memory from different cores the same memory area?

Thanks in advance,

MS

PS: The example project is attached below.

SPSW.zip

  • 0
    TI__Guru* 81335 points

    Welcome to the TI E2E forum. I hope you will find many good answers here and in the TI.com documents and in the TI Wiki Pages (for processor issues). Be sure to search those for helpful information and to browse for the questions others may have asked on similar topics (e2e.ti.com). Please read all the links below my signature.

    We will get back to you on the above query shortly. Thank you for your patience.

  • 0 in reply to Raja
    TI__Guru* 81335 points

    It sounds like you need to perform a Cache Writeback / Invalidate.  Basically, when the cache is turned on, and if you've read (cached in) the DDR memory location and then attempt to write to the DDR memory location, it's only going to be stored into the local cache until you perform a writeback from the cache to the DDR memory.  When accessing this from the DSP core, it's going to grab the 'cached' contents and not what's physically located in the DDR given that the data is cached.  While an external access will actually directly access the DDR memory interface.  And since you haven't written it back to the DDR, it's got stale data.

    Please refer below threads for more information,

  • 0 in reply to Raja
    Prodigy 20 points
    Hi Raja,

    In the .cfg I've defined a specific data section called .burstData and told to the linker to load it on DDR3. Also I've used directive DATA_SECTION to put the shared buffer BurstData[128] on the DDR3 shared section .burstData.
    This seems to work because during debugging all Cores are reading data from tha BurstData buffer placed on memory with a base address of 0x80000000 wich is tha base address of the DDR External memory on EVM6678.

    What is not working is the write back operation.

    If I invalidate the data all cores reads everytime zero! None core is writing on the DDR?

    I perform the Cache Write Back operation after modify the read data but the other processor don't recognize that. See the file src/tPlay.c of the attached projects:

    Cache_wb(pBurstData,sizeof(BurstData),Cache_Type_ALL, CACHE_WAIT);
    _mfence();

    I've also tried using:

    Cache_wbInv(pBurstData,sizeof(BurstData),Cache_Type_ALL, CACHE_WAIT);

    but using the memory browser no data are written to the external memory of the EVM6678.

    What am I forgetting to do?

    MS