Hello everyone
In the slide 9 of the above document, it shows the L2 has the same clock as CPU.
However, in the 3.2.1 stall conditions of C66x DSP Cache User Guide (page 58 in the above), it says that :"Note on the notation of stall cycles: L1D cache stall cycles for C66x devices are sometimes specified as averages due to a varying L2 clock alignment relative to the memory access. Because L2 is clocked at CORE/2, a memory access occurring out-of-phase with the L2 clock reduces the number of stall cycles by"
So which one is correct?
Thanks.
Xining
