Accessing CS2 Chip Select from u-boot

Hi,
Which memory you have connected ?
NAND or NOR ?

You have to modify the "gpmc_init" function in following file of u-boot.
u-boot/arch/arm/cpu/armv7/omap3/mem.c

Hi,

I tried to access FRAM memory from U-Boot, so i have modified GPMC_CONFIG_i registers in u-boot code and when i am trying to access that address range from u-boot CS2 also getting generated. But i am not getting anything on address lines A27--A20. I am doing this on my custom board and with AM5728 processor. I have also changed the pin mux settings for the address lines. Please check the values in the registers also, that i have configured

/****GPMC_CONFIG REGS****/
U-Boot# md 0x500000C0
500000c0: 00001000 001f1f00 001f1f01 1f011f01 ................
500000d0: 001d1f1f 08070280 00000c58

/****GPMC_PAD_CONFIG REGS****/
U-Boot# md 0x4A003440
4a003440: 00040000 00040000 00040000 00040000 ................
4a003450: 00040000 00040000 00040000 00040000 ................
4a003460: 00040000 00040000 00040000 00040000 ................
4a003470: 00040000 00040000 00040000 00040000 ................
4a003480: 00040000 00040000 00040000 00040000 ................
4a003490: 00040000 00040000 00040000 00040000 ................
4a0034a0: 00040000 00040000 00040000 00040000 ................
4a0034b0: 00060000 00060000 00060000 00060000 ................
4a0034c0: 00060000

/********U-Boot Code Change************/
--- a/arch/arm/cpu/armv7/omap-common/mem-common.c
+++ b/arch/arm/cpu/armv7/omap-common/mem-common.c
@@ -67,7 +67,23 @@ void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
(1 << 6)), &cs->config7);
sdelay(2000);
}
-
+void enable_gpmc_cs3_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
+ u32 size)
+{
+ writel(0, &cs->config7);
+ sdelay(1000);
+ /* Delay for settling */
+ writel(gpmc_config[0], &cs->config1);
+ writel(gpmc_config[1], &cs->config2);
+ writel(gpmc_config[2], &cs->config3);
+ writel(gpmc_config[3], &cs->config4);
+ writel(gpmc_config[4], &cs->config5);
+ writel(gpmc_config[5], &cs->config6);
+ /* Enable the config */
+ writel((((size & 0xF) << 8) | ((base >> 24) & 0x3F) |
+ (1 << 6)), &cs->config7);
+ sdelay(2000);
+}

/*****************************************************
* gpmc_init(): init gpmc bus
* Init GPMC for x16, MuxMode (SDRAM in x32).
@@ -77,6 +93,7 @@ void gpmc_init(void)
{
/* putting a blanket check on GPMC based on ZeBu for now */
gpmc_cfg = (struct gpmc *)GPMC_BASE;
+puts("\n gpmc_init");
#if defined(CONFIG_NOR)
/* configure GPMC for NOR */
const u32 gpmc_regs[GPMC_MAX_REG] = { STNOR_GPMC_CONFIG1,
@@ -105,8 +122,9 @@ void gpmc_init(void)
0
};
u32 base = CONFIG_SYS_NAND_BASE;
+printf("\n BASE = 0x%x",base);
u32 size = GPMC_SIZE_16M;
-
+printf("\n SIZE = 0x%x",size);
#elif defined(CONFIG_CMD_ONENAND)
const u32 gpmc_regs[GPMC_MAX_REG] = { ONENAND_GPMC_CONFIG1,
ONENAND_GPMC_CONFIG2,
@@ -138,8 +156,25 @@ void gpmc_init(void)
* Disable the GPMC0 config set by ROM code
*/
writel(0, &gpmc_cfg->cs[0].config7);
- sdelay(1000);
/* enable chip-select specific configurations */
if (base != 0)
enable_gpmc_cs_config(gpmc_regs, &gpmc_cfg->cs[0], base, size);
+ puts("\n FRAM");
+ base = 0x18000000;
+ size = 0xC;
+
+ const u32 gpmc_regs_fram[GPMC_MAX_REG] = {
+ STNOR_GPMC_CONFIG1,
+ STNOR_GPMC_CONFIG2,
+ STNOR_GPMC_CONFIG3,
+ STNOR_GPMC_CONFIG4,
+ STNOR_GPMC_CONFIG5,
+ STNOR_GPMC_CONFIG6,
+ STNOR_GPMC_CONFIG7
+ };
+
+ sdelay(1000);
+
+ enable_gpmc_cs3_config(gpmc_regs_fram, &gpmc_cfg->cs[2], base, size);
+
}

Hi,

Please check the initializations once for accessing CS2 and reply if anything wrong in the initialization process as i am not getting anything on address lines A27--A20.

Thanks & Regards,
Ganesh

Hi,
Which address are you using to access ?
Are you using the higher address space to toggle the A20-A27 lines ?

Sounds good Ganesh.
Thanks for your update.