Dear all.
We are working on C6654 and C6657 platforms (not evaluation board).
I am searching how to calculate correctly the PLLM and PLLD values for a DDR clock 66.67M in to 666.67M.
I have read the http://www.ti.com/lit/ds/symlink/tms320c6657.pdf
To calculate the PLLD and PLLM the equation CLK = CLKIN × ((PLLM+1) ÷ ((OUTPUT_DIVIDE+1) × (PLLD+1))).
But we have one equation and two unknowns. How I can calculate the PLLM and the PLLD?
Thank you in advance
George
 
				 
		 
					 
                           
				