PC read PSC and Chip-Level Registers through PCIe

From my understanding,
1. BAR0 is dedicated to Address Space 0 and BAR1~BAR5 are dedicated to Address Space 1

2. That means, the first address space (Address Space 0) is dedicated for local application registers, local configuration accesses, remote configuration accesses and remote IO accesses. The second one (Address Space 1) is dedicated for data transfer like memory (DDR, MSM) .

Thank you.

You can refer PCIe User Guide for more information,

Thank you.

Tanks for your reply.
I konw the Bar0 is dedicated and i don't use the Bar0. My problem is i can't read the 6678's address(0x02350000 - 0x0270FFFF) through PCIe.

To access PSC and chip level registers via PCIE, you need to set PCIE PRIORITY (offset 0x3C) register bit 16: MST_PRIV.

Master transaction mode. PCIe transaction needs to be in supervisor mode to access the device registers.

0 = PCIe transaction is in user mode.

1 = PCIe transaction is in supervisor mode.

Regards, Eric

Tank you, i will try it!

I have read the pciedemo.c
I set MST_PRIV bit to 1, But i can't write the MDCTL. Because i can't access the PSC regs through PCIE.

void coreLocalReset(uint32_t pid, uint32_t mid, uint32_t state)
{
uint32_t *pReg, temp, counter = 0;

/* Point to PCIE application registers */
pReg = (uint32_t *)regVirt;
/* Set MST_PRIV bit to access PSC via PCIE */
iowrite32(((ioread32(pReg + PRIORITY/4))|0x00010000), pReg + PRIORITY/4);

/* Temporarily re-map IB region 3 from DDR memory to PSC registers */
iowrite32(PSC_BASE_ADDRESS, pReg + IB_OFFSET(3)/4);
/* Now it points to the start of PSC_BASE_ADDRESS */
pReg = (uint32_t*)ddrVirt;

temp = myIoread32(pReg + MDCTL(mid)/4);
if (state == 0) {
/* Reset assert */
temp = ((temp & ~0x1F) | PSC_ENABLE) & (~0x100);
printk("Start local reset assert for core (module id): %d ...\n", mid);
} else {
/* Reset de-assert */
temp = (temp & ~0x1F) | PSC_ENABLE | (1 << 8);
printk("Start local reset de-assert for core (module id): %d ...\n", mid);
}

myIowrite32(temp, pReg + MDCTL(mid)/4); /* Assert/De-assert local reset */

/* No previous transition in progress */
counter = 0;
while (true) {
temp = myIoread32(pReg + PTSTAT/4);
if ((temp & (1 << pid)) == 0) break;
mdelay(1);
counter ++;
if (counter > 10) {
printk("Previous transition in progress pid %d mid %d state: %d\n", pid, mid, state);
break;
}
}

myIowrite32((1 << pid), pReg + PTCMD/4);

/* Current transition finished */
counter = 0;
while (true) {
temp = myIoread32(pReg + PTSTAT/4);
if ((temp & (1 << pid)) == 0) break;
mdelay(1);
counter ++;
if (counter > 10) {
printk("Current transition in progress pid %d mid %d state: %d\n", pid, mid, state);
break;
}
}

/* Verifying state change */
counter = 0;
while (true) {
temp = myIoread32(pReg + MDSTAT(mid)/4);
if ((temp & 0x1F) == 3) break;
mdelay(1);
counter ++;
if (counter > 10) {
printk("MD stat for pid %d mid %d state: %d timeout\n", pid, mid, state);
break;
}
}

/* Restore pointer */
pReg = (uint32_t *)regVirt; /* Point to PCIE application registers */
iowrite32(DDR_START, pReg + IB_OFFSET(3)/4);
}

Hi,

Have you using Linux or windows Host PC for your setup? The Linux host loader Example only works on Linux PC.

Thanks,

I use Windriver ,the os is windows 7.

Hi,

TI has validated this demo code on Linux PC.

Thanks,