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am3352 DDR3 refresh rate configuration

Joe Chen3
Intellectual 480 points
Other Parts Discussed in Thread: AM3352

Hi experts,

I use am3352 as our main CPU and H5TQ2G63FFR-PBC as DDR3 RAM.

I want to test DDR3 reliability in high temperature environment.

Following information comes from DDR3 datasheet.

Average Refresh Cycle (Tcase 0 oC~ 95oC)
- 7.8 µs at 0oC ~ 85 oC
- 3.9 µs at 85oC ~ 95 oC

For this testing.
Is it enough for me to set 0x618(400M * 3.9us) to "reg_refresh_rate" and set 1 to "reg_srt" in register "SDRAM_REF_CTRL" ? or something I am not aware of?

thanks.
dipsy

  • 0
    TI__Guru*** 125430 points

    Joe Chen3 said:
    Is it enough for me to set 0x618(400M * 3.9us) to "reg_refresh_rate"

    That is correct.

    Joe Chen3 said:
    and set 1 to "reg_srt" in register "SDRAM_REF_CTRL" ? or something I am not aware of?

    The reg_srt bitfield pertains to "self refresh temperature".  In other words, this is not something that pertains to the AM335x sending refresh commands every 3.9us.  This bitfield relates to how the DDR3 behaves in self-refresh.  This setting doesn't control anything in the AM335x.  It is used to program Mode Register 2, bit 7, of the DDR3 device.  Please see the JEDEC DDR3 specification for more details on this bit.  It is an optional bit, so not all DDR3 memories will support this capability.