prioritization of access to EMIF16 on C66xx

Hi

I am looking for a way to prioritize the acces to EMIF16 so that my EDMA3 transfer gets access to EMIF16 before the Core.

I have a low priority task that writes a large amount of data to EMIF16 using a simple loop like this

low_prio_task()
{
  uint16* EMIF = EMIF_ADDR;
  while(1)
  {
    SEM_PEND(some_semaphore)  
    for(i = 0; i < size; i++)
    {
      EMIF16[i] = data[i];
      index++;
    }
  }
}

And I have setup a EDMA3 channel to read data fra EMIF16 to internal L2_RAM when triggered by an event from a GPIO. The GPIO triggers the EDMA at a relatively high frequency, and it important for the system that the data are read as soon as possible.

The problem is that the EDMA transfer does not begin reading data until the low_prio_task has finished writing its data, and that gives such a large delay in the system data loop that it does not work properly.

I would like to know if there is a way to configure either EMIF og EDMA3 so that the DMA gets access to EMIF at once.

I am running on a C6655 using CCS6.10

Best

Jens