AM3359 pin muxing

Terry Fryar

In looking at the AM335x TRM, the memory map table 9-10, CONTROL_MODULE registers...I notice that at offset 0x800 is where the control registers start for gpio bank1, pin 1. I assume these are in order by bank and pin? Where are the registers then, for GPIO bank 0?

over 10 years ago

0 Yordan Kovachev over 10 years ago

TI__Guru**** 161600 points

Hi Terry,

Memory map just shows the base address of CONTROL_MODULE registers. You can find the offsets of the pinmux (conf_<pin_name>) registers in Table 9-10. CONTROL_MODULE REGISTERS (continued) in Control Module chapter.
You should also check Table 4-1. Ball Characteristics (ZCE and ZCZ Packages) in device Data Manual, to see on which ball you can mux the corresponding pins.

Best Regards,
Yordan

0 Terry Fryar over 10 years ago in reply to Yordan Kovachev

Prodigy 175 points

Yes, I use the 9-10 table all the time, but I cannot find the GPIO bank 0 registers? Let me rephrase the question....is the 9-10 table in order by bank and gpio pin number?

0 Yordan Kovachev over 10 years ago in reply to Terry Fryar

TI__Guru**** 161600 points

In device DATA MANUAL, Table 4-1. Ball Characteristics (ZCE and ZCZ Packages), search for gpio0. The PIN NAME column of Table 4-1 is the name of the register you should search for in Table 9-10.

I.e. to mux gpio0_2 on a device pad, you should set conf_spi0_sclk[2:0] to 0x7.

Best Regards,

Yordan

0 Terry Fryar over 10 years ago in reply to Yordan Kovachev

Prodigy 175 points

Yes, I am quite aware of how to set control registers on a 335x, I do it all the time. All I wanted to know is how the 9-10 table was ordered. You did not answer my question....oh well....thanks anyways!

0 Yordan Kovachev over 10 years ago in reply to Terry Fryar

TI__Guru**** 161600 points

It is ordered by incrementing address offsets. The gpio bank/pin numbers or any other IP numbering is not considered.

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AM3359 pin muxing