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Changing EVM6670LE input clock frequency

Hari..
Intellectual 605 points

Other Parts Discussed in Thread: CDCE62005

Hi,

I am working on EVM6670LE which has 122MHz as sysclk and 250MHz clock for SRIO. Section 2.4 of TMDXEVM6670L EVM Technical Reference Manual(SPRUH59) says external reference clocks are supported starting Rev 3.0. So I am looking to program 153.6 as sysclk and 312.5 MHz for SRIO Clk. But the exact procedure is not clear to me. Can someone help me in programming the external reference clocks on EVM6670LE ?


Regards,

Hari

  • 0
    TI__Mastermind 43660 points
    Hello Hari,

    I think you misunderstood the statement given in section 2.4. The external clock is meant for AIF and HyperLink SerDes interfaces. The external clocks is driven into the clock generator rather than using a crystal.

    Your interpretation towards changing the SYSCLK and SRIOCLK outputs from the clock generator is not correct. The CDCE clock generators on the EVM is programmed at power-on by the FPGA. There is no external programming interface. The DSP can write to registers in the FPGA to change the clock programming.

    Please refer section 5.5.3 The FPGA- programming CDCE62005 / 62002 by the DSP in TMDXEVM6670L EVM Technical Reference Manual(SPRUH59) for programming the clock generator through FPGA.

    Regards,
    Senthil