AM335x LCD timings

Jake Pulliam

Other Parts Discussed in Thread: TFP410

I am looking to interface a Texas Instruments TFP410 DVI Transmitter with a Sitara AM335x series microprocessor. The timing requirements for the TFP410 are 1.2ns for Tsu (setup time) and 1.3ns for Th (hold time).

In order to make sure the Sitara can meet those requirements (I assume it can but I need to show it in writing) I am trying to find the timing information in the data sheet (TI Doc SPRS717H). I am looking at section 7.10.2, Table 7-76 “Switching Characteristics for LCD Raster Mode” but I’m unclear on how to interpret the data in the table in order to verify the timing requirement can be met. How can I calculate data valid time before clock transition (setup) and data valid time after clock transition (hold) based on the supplied data?

Thanks for your help.

over 11 years ago

0 Yordan Kovachev over 11 years ago

TI__Guru**** 161600 points

Hi Jake,

Your query is being looked at.
I've also consulted the design team.

Best Regards,
Yordan

0 Jake Pulliam over 11 years ago in reply to Yordan Kovachev

TI__Expert 6520 points

Thanks Yordan. Has there been any progress on this?

Jake

0 Yordan Kovachev over 11 years ago in reply to Jake Pulliam

TI__Guru**** 161600 points

Hi Jake,

No response yet.

I've sent a reminder to the design team. Their feedback will be posted here.

Best Regards,
Yordan

0 peaves over 11 years ago in reply to Yordan Kovachev

TI__Guru 64835 points

The data sheet provides worst case output delays of LCD data relative to the pixel clock. LCD data can be configured to change on the rising or falling edge of the pixel clock. Parameter number 4 defines the maximum time it takes for LCD data to become valid after the selected clock edge. Parameter number 5 defines the maximum time where LCD data becomes invalid before the selected clock edge. So in the OPP100 use case, LCD data may begin to change as early as 1.7ns before the selected clock edge and is not guaranteed to be valid until 1.9ns after the selected clock edge.

You should be able to use this information along with pixel clock period and PCB delays to determine the minimum setup and hold times provided to the DVI transmitter.

Regards,
Paul

0 Jake Pulliam over 11 years ago in reply to peaves

TI__Expert 6520 points

Thanks for the information. That helps me out.

Jake

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AM335x LCD timings