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AM335 GPMC_WAIT0 & GMII2_CRS muxing - NAND boot issue

Guillaume HENRI
Prodigy 10 points


Dear TI support,

An AM335x design implements an external mux as workaround for “Multiplexed Signals GPMC_WAIT0 and GMII2_CRS Cause NAND Boot Issue” described in the errata.

As a first step the GPMC_CLK signal has been used as external Mux control IO but unfortunately this signal is driven to "low" by the rom code during the boot which makes the boot up from NAND fail

It would be then interesting then to know what pins could be used or not to drive the external mux  …

So the question is what IO are driven/affected by the rom code during the AM335x boot and which could not be used as mux control signal?

Thank you

Best regards,

Guillaume

 

  • 0
    TI__Guru**** 161600 points

    Hi Guillaume,

    Guillaume HENRI said:
    So the question is what IO are driven/affected by the rom code during the AM335x boot and which could not be used as mux control signal?

    You can check Sections 26.1.6 Fast External Booting through 26.1.8 Peripheral Booting. For every boot mode there is a Pins Used subsection, which shows the device pads configured & used by the ROM Code. 

    Best Regards, 

    Yordan