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Cannot detect CER bit set when perform DMA chain-triggered.

Peter010
Genius 4165 points

Hi everyone

What I want to do is following the section 3.3 Data Sorting Example. I am using EDMA 1 in global region. I am using Chip Support Library.  The following is the configuration of Chain trigger register. In order to make the transmission successfully, I have to debug step by step in the step 7. If I run the program without stopping, data transmission would be failed (EMR would be set in corresponding bit and no data would arrived at receiving buffer). No matter in which condition (debug or running), I cannot see CER bit is set ( I enable ITCCHEN).

Also, can anyone send me a chain trigger example project to me?

Thanks

Xining

1. 

/* Map Channel to EDMA 1 */

CSL_edma3HwChannelSetupQue(hChannel,CSL_EDMA3_QUE_1)

2.

/* Map the DMA Channel to PARAM Block 1. */
CSL_edma3MapDMAChannelToParamBlock (hModule, channelNum, 1)；

3.

/* Obtain a handle to parameter set 1 */
hParam = CSL_edma3GetParamHandle(hChannel, 1, &status);

4.

/* Setup the parameter entry parameters */
myParamSetup.option = CSL_EDMA3_OPT_MAKE(CSL_EDMA3_ITCCH_EN, \
CSL_EDMA3_TCCH_DIS, \
CSL_EDMA3_ITCINT_DIS, \
CSL_EDMA3_TCINT_EN, \
10, CSL_EDMA3_TCC_NORMAL,\
CSL_EDMA3_FIFOWIDTH_NONE, \
CSL_EDMA3_STATIC_DIS, \
CSL_EDMA3_SYNC_AB, \
CSL_EDMA3_ADDRMODE_INCR, \
CSL_EDMA3_ADDRMODE_INCR );
myParamSetup.srcAddr = src;
myParamSetup.aCntbCnt = CSL_EDMA3_CNT_MAKE(ACount,BCount);
myParamSetup.dstAddr = dst;
myParamSetup.srcDstBidx = CSL_EDMA3_BIDX_MAKE(ACount,ACount*CCount);
myParamSetup.linkBcntrld= CSL_EDMA3_LINKBCNTRLD_MAKE(0XFFFF,0);
myParamSetup.srcDstCidx = CSL_EDMA3_CIDX_MAKE(ACount*BCount,ACount);
myParamSetup.cCnt = CCount;

5.

CSL_edma3ParamSetup(hParam,&myParamSetup)

6.

/* Interrupt enable (Bits 0) for the global region interrupts */
regionIntr.region = CSL_EDMA3_REGION_GLOBAL;
regionIntr.intr = 0x1;
regionIntr.intrh = 0x0000;
CSL_edma3HwControl(hModule,CSL_EDMA3_CMD_INTR_ENABLE,&regionIntr);

7.

while(CCount--)

{
/* Trigger channel */
CSL_edma3HwChannelControl(hChannel,CSL_EDMA3_CMD_CHANNEL_SET,NULL);
}

The following two figures is explanation of data sorting example from user manual.

  • 0
    TI__Mastermind 35645 points

    Hi,

    Thanks for your post.

    I have few suggestions:

    Please, ensure first whether TCCHEN bit is enabled in channel OPT and only then, the interrupt pending register (IPR / IPRH) relevant bit position appropriate to the DMA event would be set on transfer completion

    Also, ensure the TCCMODE bit in OPT which would indicate normal or early completion of data transfer and again, I would suggest you to validate the received TCC code in OPT first on the triggered DMA channel and accordingly, the corresponding bit position in IPR/IPRH would be set which is directly the TCC value and thereafter, the corresponding CER[TCC] / CERH [TCC] bit would be set to generate a EDMA completion interrupt to the DSP. By the way, the same 6-bit TCC would be posted by the TC to the CC after it receives the transfer completion signal from the destination peripheral in normal completion mode. Have you checked this?

    Please check the below keystone edma tutorials:

    http://www.ti.com/lit/ug/sprugs5b/sprugs5b.pdf

    http://processors.wiki.ti.com/images/b/b8/Eindhoven_JAN_12-10_IntroTo_Edma.pdf?keyMatch=EDMA

     

    Thanks & regards,

    Sivaraj K

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  • 0 in reply to Sivaraj Kuppuraj
    Genius 4165 points

    Hi Sivaraj

    From the training material, I found the problem is the TCC bit should be the channel number supposed to be triggered next. In my case, TCC should be the same as the first transmitting channel. However, previously, I randomly choose TCC bit. The randomly choose TCC bit would not trigger the next chain channel. However, even if I set the wrong TCC bit, I can do multiply manual trigger to finish the reset of Chain-triggered transmission.


    Xining