Question about 66AK2H14 EVM 122.88M clock.

Denny%20Yang99373

Other Parts Discussed in Thread: 66AK2H14

Hi team,

There are three 122.88M clock input for 66AK2H14, they are SYSCLK_P/N,TSREFCLK_P/N and PASSCLK_PN, need phase alignment with any other clocks such as XFI, PCIE, USB clocks? Do I need generate these 122.88M clocks from same clock source with other clocks?

BR,
Denny

over 10 years ago

0 Senthilkumar Srinivasan over 10 years ago

TI__Mastermind 43660 points

Hello Denny,

It is not necessary that the clocks of the DSP be synchronous or phase aligned. There is no requirement to use the same clock source for clock generation. Please refer clocking section in Keystone2 hardware design guide for clocking requirements.

Regards,
Senthil

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Question about 66AK2H14 EVM 122.88M clock.