Adding DDR3 changes to AM33xx SoC using MT41K128M16JT-125:K part-number

vamshi krishna gajjela said:

To my understanding the major differnce bettwen these to different parts is the speed, so what all the parameters I have to  look into data sheet, for adding support to MT41K128M16JT-125:K

You should be able to use the DDR Calculation Tool to generate the appropriate register settings for this memory:

http://processors.wiki.ti.com/index.php/AM335x_EMIF_Configuration_tips

vamshi krishna gajjela said:

and where do we mention the size of DDR whther it is 512 or 256 ?

That should be reflected in the SDRAM_CONFIG register (number banks, number column address bits, etc.)

Hi Brad,

Thanks for the information, and it is very useful.

I have download AM335x_DDR_register_calc_tool.xls

It looks, the excel AM335x_DDR_register_calc_tool.xls is generating vales for the registers EMIF_TIM1, EMIF_TIM2, EMIF_TIM3. Correct me if I am wrong. These values are said as optimized register values, how which will it be the consequence ? for example if tRP is 13.125 in data-sheet and I enter the rounded value 13 in xls.

How do I calculate the values for the rest of the registers based on the DDR3 part I used MT41K128M16JT-125:K.
EMIF_READ_LATENCY, EMIF_SDCFG,
EMIF_SDREF
ZQ_CFG
RATIO
INVERT_CLKOUT
RD_DQS
WR_DQS
PHY_WR_DATA
PHY_FIFO_WE
IOCTRL_VALUE

Thanks in advance.

Most of these are described here:

http://processors.wiki.ti.com/index.php/AM335x_EMIF_Configuration_tips

The remainder relate to leveling and are discussed here:

http://processors.wiki.ti.com/index.php/AM335x_DDR_PHY_register_configuration_for_DDR3_using_Software_Leveling

Hi Brad,

Above links helped me to some extent, I have went through data sheet and identified the following values.

This is the part number of the DDR3 I have interfaced to AM3352 MT41K128M16JT-125:K

• CAS Read Latency (CL) = 11
• CAS Write Latency (CWL) = 8
• tCK = 1.25

Using these values I have worked to prepare SDRAM_CONFIG looking into AM33xx TRM. I need some of the inputs from you.

• 31-29 = 3 (Since it is DDR3)
• 28-27 = 0 (Internal Bank Position, set to 0 to access the maximum number of banks to be open )
• 26-24 = 1 (For DDR3, set to 1 for RZQ/4, need your inputs here, is this the ZQ resistor and it RZQ/4 should be equal to which value? )
• 23       = 1 (DDR2 and LPDDR2 differential DQS enable)
• 22-21 = 1 (DDR3 Dynamic ODT), do we need to Dynamic ODT, if yes what value has to be chosen, 1 for RZQ/4, 2 for RZQ/2)
• 20       = 0 (Do not disable DLL)
• 19-18 = 0 (SDRAM drive strength, how do I choose this ? For DDR3, set to 0 for RZQ/6 and set to 1 for RZQ/7. )
• 17-16 = 3 (since CWL=8)
• 15-14 = 1 (since 16 bit bus)
• 13-10 = 14 (0xE) (since CAS = 11) is this anything wear having
• 9-7     = 5 (since 14 bit row)
• 6-4     = 3 (since 8 bank)
• 3         = 0 (external bank select, I understand it is 0, need your inputs)
• 2-0     = 2 (since 10 column bits)

This gives me a SDRAM_CONFIG value = 0x61A37AB2

Coming to the Timing values based on the data sheet

tCK          1.25
tRP          13.75
tRCD       13.75
tWR         15
tRAS       36
tRC         48.75
tRRD      4
tWTR      4
tXP          3
ODTLon    3
tXS          170
tXSDLL    512
tRTP    4
tCKE    3   
tZQCS    64
tRFC    160

I got the following values,

#define MT41K128M16JT125K_EMIF_TIM1        0x1557C99B
#define MT41K128M16JT125K_EMIF_TIM2        0x26877FDA
#define MT41K128M16JT125K_EMIF_TIM3        0x501F87FF

#define MT41K128M16JT125K_EMIF_READ_LATENCY    0x10000C // 11 + 2 -1 = 12 (CL=11) is there any thing wrong here

but I suspect the DDR3 initialization is not happening fine ? because it is failing just before call to spl_board_init which is called from board_init_r, I understand this expects DDR3 initialized by this time.

I am working to configure DDR3 at 400MHz, but these values are give for DDR3L-1600 Speed Bin, how do I make them for 400MHz

Please need your inputs.

vamshi krishna gajjela said:

• CAS Read Latency (CL) = 11
• CAS Write Latency (CWL) = 8
• tCK = 1.25

tCK = 1.25ns corresponds to an 800 MHz clock (DDR3-1600).  You are mixing up the device rating with the actual bus frequency.  Although you're using a DDR3-1600 device, you need to do all the calculations based on your actual bus frequency of 400 MHz (tCK = 2.5 ns).  If you go into the DDR3 data manual and look at Table 54 (DDR3L-1600 Speed Bins), this information is shown explicitly.  In particular, there is a row that shows the timings for tCK (AVG) with a min of 2.5 ns and a max of 3.3ns.  That's the timings you need...  Thtat means you should be using CL=6 and CWL=5.

vamshi krishna gajjela said:

• 26-24 = 1 (For DDR3, set to 1 for RZQ/4, need your inputs here, is this the ZQ resistor and it RZQ/4 should be equal to which value? )
• 23       = 1 (DDR2 and LPDDR2 differential DQS enable)
• 22-21 = 1 (DDR3 Dynamic ODT), do we need to Dynamic ODT, if yes what value has to be chosen, 1 for RZQ/4, 2 for RZQ/2)

There's not a single answer here...  If you use only dynamic ODT you can reduce your power consumption but you also have less configurability in terms of the values.  If you use only the nominal ODT it will consume a bit more power but give you greater flexibility.  In terms of picking the optimal value I would suggest IBIS modeling.  If you don't plan on using IBIS modeling you may want to just use the same as the EVM.

vamshi krishna gajjela said:

19-18 = 0 (SDRAM drive strength, how do I choose this ? For DDR3, set to 0 for RZQ/6 and set to 1 for RZQ/7. )

IBIS modeling is preferred.  I would copy the EVM as a fallback.

vamshi krishna gajjela said:

#define MT41K128M16JT125K_EMIF_TIM1        0x1557C99B
#define MT41K128M16JT125K_EMIF_TIM2        0x26877FDA
#define MT41K128M16JT125K_EMIF_TIM3        0x501F87FF

Were these computed using tCK = 2.5ns in the spreadsheet?

vamshi krishna gajjela said:

#define MT41K128M16JT125K_EMIF_READ_LATENCY    0x10000C // 11 + 2 -1 = 12 (CL=11) is there any thing wrong here

Clearly this will need to be updated for your proper CAS latency.  I would add one additional cycle of margin here, i.e. just use CL + 2 for this field.

Hi Brad,

I am very happy with your inputs. Would like to clarify few of the things.

1) Iam not sure about IBIS modeling. Assuming power consumption is not a issue, what values we can choose for

26-24 = 1?

23       = 1?

22-21 = 1?

19-18 = 0?

2) Values I computed are with tCK 1.25, I will recalculate with tCK 2.5,

3) with CL=6 then  #define MT41K128M16JT125K_EMIF_READ_LATENCY  0x8

4) You mentioned you would use EVM as fallback ? which EVM you are referring to. Please share those values.

5) In case of calculating the Ratios

DDR_CK trace    1.653543307    1.653543307
DDR_DQSx trace    1.700787402    1.614173228  (this different length for Byte-0 & Byte-1 will have any effect)

In this case PHY_INVERT_CLKOUT    1

Intermediate values (per byte lane)        
WR DQS    7F    80
RD DQS    40    40
RD DQS GATE    11D    119
        
Seed values used in CCS code        
DATAx_PHY_RD DQS_SLAVE_RATIO    40    
DATAx_PHY_FIFO_WE_SLAVE_RATIO    11B    
DATAx_PHY_WR DQS_SLAVE_RATIO    7F    
        
Register value        
CMDx_PHY_CTRL_SLAVE_RATIO    100    


Do you want me to use the values obtained form the Ratio_Seed excel here ?

Correct me If I am missing any thing.

Thanks & Regards,

Vamshi G.

vamshi krishna gajjela said:

23       = 1?

This is the differential DQS control.  Yes, since the DDR3 has both DQS and DQS# signals you must set this bit to 1.

vamshi krishna gajjela said:

22-21 = 1?

I would set dynamic ODT to zero (disabled) since you have already configured the nominal ODT.

vamshi krishna gajjela said:

26-24 = 1?

19-18 = 0?

These are reasonable, i.e. same as EVM.

vamshi krishna gajjela said:

2) Values I computed are with tCK 1.25, I will recalculate with tCK 2.5,

Ok, that's good.

vamshi krishna gajjela said:

3) with CL=6 then  #define MT41K128M16JT125K_EMIF_READ_LATENCY  0x8

Correct.

vamshi krishna gajjela said:

4) You mentioned you would use EVM as fallback ? which EVM you are referring to. Please share those values.

I'm referring to the AM335x EVM.  There is quite a bit of this already in u-boot in the file arch/arm/include/asm/arch-am33xx/ddr_defs.h.  For example, I see what looks to be nearly the same device as you're using:

/* Micron MT41K128M16JT-187E */
#define MT41K128MJT187E_EMIF_READ_LATENCY       0x06
#define MT41K128MJT187E_EMIF_TIM1               0x0888B3DB
#define MT41K128MJT187E_EMIF_TIM2               0x36337FDA
#define MT41K128MJT187E_EMIF_TIM3               0x501F830F
#define MT41K128MJT187E_EMIF_SDCFG              0x61C04AB2
#define MT41K128MJT187E_EMIF_SDREF              0x0000093B
#define MT41K128MJT187E_ZQ_CFG                  0x50074BE4
#define MT41K128MJT187E_RATIO                   0x40
#define MT41K128MJT187E_INVERT_CLKOUT           0x1
#define MT41K128MJT187E_RD_DQS                  0x3B
#define MT41K128MJT187E_WR_DQS                  0x85
#define MT41K128MJT187E_PHY_WR_DATA             0xC1
#define MT41K128MJT187E_PHY_FIFO_WE             0x100
#define MT41K128MJT187E_IOCTRL_VALUE            0x18B

To be honest I'm not sure if these were created by TI or if this was someone else's contribution to u-boot.  I would take these as a data point and if your calculations differ then you should dig a bit deeper to be sure.

vamshi krishna gajjela said:

Intermediate values (per byte lane)        
WR DQS    7F    80
RD DQS    40    40
RD DQS GATE    11D    119
        
Seed values used in CCS code        
DATAx_PHY_RD DQS_SLAVE_RATIO    40    
DATAx_PHY_FIFO_WE_SLAVE_RATIO    11B    
DATAx_PHY_WR DQS_SLAVE_RATIO    7F    
        
Register value        
CMDx_PHY_CTRL_SLAVE_RATIO    100    


Do you want me to use the values obtained form the Ratio_Seed excel here ?

Yes.

Hi Brad,

Regarding Ratios here is the link http://processors.wiki.ti.com/index.php/AM335x_EMIF_Configuration_tips

I have tried with the previous changes for the Timing and the SDRAM_CONFIG, there is no Luck, I am trying to bring the board over UART boot, it is able to load

u-boot-spl.bin over UART and failing to acknowledge 'C'

I understand that arch/arm/lib/ctr0.s invokes board_init_f, this in turn calls board_early_init_f and sdram_init. After the initialization of SDRAM, board_init_r is

invoked, and this expects that SDRAM is initialized by the time, but I am seeing a hang after this point. I am debugging with the LEDs I have on the board.

This hangs give me impression that DDR is not properly initialized, correct me if I am wrong. Please let me know if I am missing any thing vital in this bring-up

process.

Here are the values

/* Micron MT41K128M16JT-125K */

#define MT41K128M16JT125K_EMIF_READ_LATENCY    0x08

#define MT41K128M16JT125K_EMIF_TIM1        0x0AAAE4DB

#define MT41K128M16JT125K_EMIF_TIM2        0x26437FDA

#define MT41K128M16JT125K_EMIF_TIM3        0x501F83FF

#define MT41K128M16JT125K_EMIF_SDCFG        0x610052B2

#define MT41K128M16JT125K_EMIF_SDREF        0x0000093B

#define MT41K128M16JT125K_ZQ_CFG        0x50074BE4

#define MT41K128M16JT125K_RATIO            0x40

#define MT41K128M16JT125K_INVERT_CLKOUT        0x1

#define MT41K128M16JT125K_RD_DQS        0x40

#define MT41K128M16JT125K_WR_DQS        0x85

#define MT41K128M16JT125K_PHY_WR_DATA        0x7F

#define MT41K128M16JT125K_PHY_FIFO_WE        0x11B

#define MT41K128M16JT125K_IOCTRL_VALUE        0x18B

Please give your inputs.

Hi Brad,

Regarding Ratios here is the link http://processors.wiki.ti.com/index.php/AM335x_EMIF_Configuration_tips

And the tool to  calculate the ratios is available for the link.

In order to run the software leveling code you should have modified the gel file to use the timing parameters you mention here.  Were those functional?  In other words you should have done the following:

1. Updated the gel file with your parameters.
2. Connected to the Cortex A8 which should then run the gel file to initialize the DDR3.
3. Open a memory window to 0x80000000.  Can you write data into DDR3?  Does it "stick" when you refresh the memory window?
4. Run the software leveling code.
5. Take your AC timings and your leveling results and put all that into u-boot.