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AM335x GPMC WAIT Pins Handling at Boot

Tsutomu Furuse
Expert 1435 points

Hi.

One of my customers would like to use the AM335x Non-Muxed XIP_MUX2 mode for NOR boot.
I have two questions about the WAIT pins handling for the boot.

  1. If we prefer the XIP with WAIT mode although we don't use the WAIT feature, do we need to pull-up both WAIT0(GPMC_WAIT0) and WAIT1(GPMC_CLK)?
  2. If we prefer the XIP without WAIT mode, can we use the GPMC_WAIT pin and the GPMC_CLK pin as GPIO?
    (I'd like to know if the public ROM code changes the PINMUX for the WAIT pins at the XIP without WAIT mode.)

Best regards,
Tsutomu Furuse

  • 0
    TI__Guru**** 393215 points

    Hi,

    Tsutomu Furuse said:
    If we prefer the XIP with WAIT mode although we don't use the WAIT feature, do we need to pull-up both WAIT0(GPMC_WAIT0) and WAIT1(GPMC_CLK)?

    Only WAIT0 needs a pullup.

    Tsutomu Furuse said:
    If we prefer the XIP without WAIT mode, can we use the GPMC_WAIT pin and the GPMC_CLK pin as GPIO?
    (I'd like to know if the public ROM code changes the PINMUX for the WAIT pins at the XIP without WAIT mode.)

    GPMC_WAIT0 is initialized to GPMC mode by the ROM code in all XIP modes. GPMC_CLK is not initialized in XIP_MUX2 mode. GPMC_WAIT1 is not initialized in XIP_MUX1 mode. Please refer to Table 26-9 in the AM335X TRM Rev. L.

  • 0 in reply to Biser Gatchev-XID
    Expert 1435 points

    Biser,

    Thank you for the answer.

    GPMC_WAIT0 is initialized to GPMC mode by the ROM code in all XIP modes. GPMC_CLK is not initialized in XIP_MUX2 mode. GPMC_WAIT1 is not initialized in XIP_MUX1 mode. Please refer to Table 26-9 in the AM335X TRM Rev. L.

    From the table you mentioned, I understand that both the GPMC_WAIT0 pin and the GPMC_CLK pin in XIP_MUX2 are initialized.

    Best regards,
    Tsutomu Furuse

  • 0 in reply to Tsutomu Furuse
    TI__Guru**** 393215 points

    Correct, however note that for XIP_MUX2:

    GPMC_WAIT0 pin is initialized to GPMC_WAIT0 mode

    GPMC_WAIT1 pin is initialized to GPMC_CLK mode

    GPMC_CLK pin is not initialized (is left in default mode).

  • 0 in reply to Biser Gatchev-XID
    Expert 1435 points

    Biser,

    Thank you for your quick reply.

    I'm getting confused.

    I understand "Signal name" column of the table means the GPMC signal function and "Pin used in XIP_MUX2 mode" column means the physical pin.
    So I suppose that:

    • GPMC_WAIT0 pin (ZCE: R15 / ZCZ: T17) is initialized to the WAIT0 function pin.
    • GPMC_CLK pin (ZCE: V16 / ZCZ: V12) is initialized to the WAIT1 function pin.
    • No pin is initialized to the CLK function pin because the XIP_MUX2 mode is used with asynchronous device.

    Please correct me if I'm wrong.

    Best regards,
    Tsutomu Furuse

  • 0 in reply to Tsutomu Furuse
    Expert 1435 points

    Stricly speaking, I understand as follows:

    • The PINMUX setting of GPMC_WAIT0 pin (ZCE: R15 / ZCZ: T17) is initialized to the mode 0 (gpmc_wait0).
    • The PINMUX setting of GPMC_CLK pin (ZCE: V16 / ZCZ: V12) is initialized to the mode 2 (gpmc_wait1).
    • No pin is initialized to the CLK function pin because the XIP_MUX2 mode is used with asynchronous device.

    Best regards,
    Tsutomu Furuse

  • 0 in reply to Tsutomu Furuse
    TI__Guru**** 393215 points

    Tsutomu Furuse said:
    I understand "Signal name" column of the table means the GPMC signal function and "Pin used in XIP_MUX2 mode" column means the physical pin.

    It's the opposite - "Signal name" column of the table means the physical pin and "Pin used in XIP_MUX2 mode" column means the GPMC signal function.

  • 0 in reply to Biser Gatchev-XID
    Expert 1435 points

    Biser,

    So, how do you explain the A0-A11 signal name rows?

    I suppose that the public ROM code initialize these LCD pins for GPMC addess with PINMUX mode 1.

    Signal Name
    in PINMUX Mode 1    		 Pin
    gpmc_a0 LCD_DATA0
    gpcm_a1 LCD_DATA1
    gpmc_a2 LCD_DATA2
    gpmc_a3 LCD_DATA3
    gpmc_a4 LCD_DATA4
    gpmc_a5 LCD_DATA5
    gpmc_a6 LCD_DATA6
    gpmc_a7 LCD_DATA7
    gpmc_a8 LCD_VSYNC
    gpmc_a9 LCD_HSYNC
    gpmc_a10 LCD_PCLK
    gpmc_a11 LCD_AC_BIAS_EN

    Best regards,
    Tsutomu Furuse

  • 0 in reply to Tsutomu Furuse
    TI__Guru**** 393215 points

    Sorry, my mistake in the last post I made. You are right of course.

  • 0 in reply to Biser Gatchev-XID
    Expert 1435 points

    Biser,

    Thank you for your confirmation.

    Best regards,
    Tsutomu Furuse