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DDR3 problem

giorgos tsoumplekas
Expert 1840 points

Dear all,

We are working on a C6654 platform that has a DDR3 clock  is synchronized at 1333 MHz. The chip is a micron one 16 Meg x 16 x 8 banks.

The input clock is at 66.67MHz. We  load the image using a bootloader firmware that download the final image using  PCIe,  as in the examples that  are provided in the mcsdk_2_01_02_06 .

For configre the PLL and DDR3  we used the code that is provided by TI under pdk6657 folder and we have modified this  to be align with the clock specification for the C6654 clock.

When the program starts the DDR3 is initialized and stable. But when we access a specific region of memory and initialized some addresses with the value  -1 , 0xFFFF_FFFF hex we noticed that   some values of this section periodically  changes one specific bit from  1 to 0.

It is the same bit for all the address, the 16bit in the sequence.

For instance instead of   0xFFFF_FFFF we have 0xFFFD_FFFF. The program is halted and no interrupts runs in the system  at the time that the values changes.

We have already run a program that test the DDR3 and no error has occurred when read/write from and to DDR3.

 

Could please give us any hint what probably goes wrong?

//NOTE: code that we use for the DDR3 initialization, provided by TI without any change
CSL_Status DDR3Init()
{

    CSL_Status status = CSL_SOK;
    volatile unsigned int loopCount;
    uint32_t ddr3config, ddrPhyCtrl;
    uint8_t ddrPHYReadLatency;
    EMIF4F_TIMING1_CONFIG sdram_tim1;
    EMIF4F_TIMING2_CONFIG sdram_tim2;
    EMIF4F_TIMING3_CONFIG sdram_tim3;
    EMIF4F_OUTPUT_IMP_CONFIG    zqcfg;
    EMIF4F_PWR_MGMT_CONFIG      pwrmgmtcfg;
    EMIF4F_SDRAM_CONFIG         sdramcfg;

    CSL_BootCfgUnlockKicker();

    /* Wait for PLL to lock = min 500 ref clock cycles.
       With refclk = 100MHz, = 5000 ns = 5us */
    platform_delaycycles(50000);

    /**************** 3.3 Leveling Register Configuration ********************/
    CSL_BootCfgGetDDRConfig(0, &ddr3config);
    ddr3config &= ~(0x007FE000);  // clear ctrl_slave_ratio field
    CSL_BootCfgSetDDRConfig(0, ddr3config);

    CSL_BootCfgGetDDRConfig(0, &ddr3config);
    ddr3config |= 0x00200000;     // set ctrl_slave_ratio to 0x100
    CSL_BootCfgSetDDRConfig(0, ddr3config);

    CSL_BootCfgGetDDRConfig(12, &ddr3config);
    ddr3config |= 0x08000000;    // Set invert_clkout = 1
    CSL_BootCfgSetDDRConfig(12, ddr3config);

    CSL_BootCfgGetDDRConfig(0, &ddr3config);
    ddr3config |= 0xF;            // set dll_lock_diff to 15
    CSL_BootCfgSetDDRConfig(0, ddr3config);

    CSL_BootCfgGetDDRConfig(23, &ddr3config);
    ddr3config |= 0x00000200;    // See section 4.2.1, set for partial automatic levelling
    CSL_BootCfgSetDDRConfig(23, ddr3config);

    /**************** 3.3 Partial Automatic Leveling ********************/
    ddr3config = 0x00;        CSL_BootCfgSetDDRConfig(2,  ddr3config);
    ddr3config = 0x00;        CSL_BootCfgSetDDRConfig(3,  ddr3config);
    ddr3config = 0x00;        CSL_BootCfgSetDDRConfig(4,  ddr3config);
    ddr3config = 0x00;        CSL_BootCfgSetDDRConfig(5,  ddr3config);
    ddr3config = 0x00000033;  CSL_BootCfgSetDDRConfig(6,  ddr3config);
    ddr3config = 0x0000003A;  CSL_BootCfgSetDDRConfig(7,  ddr3config);
    ddr3config = 0x0000002C;  CSL_BootCfgSetDDRConfig(8,  ddr3config);
    ddr3config = 0x0000002C;  CSL_BootCfgSetDDRConfig(9,  ddr3config);
    ddr3config = 0x0000001C;  CSL_BootCfgSetDDRConfig(10, ddr3config);

    ddr3config = 0x00;        CSL_BootCfgSetDDRConfig(14,  ddr3config);
    ddr3config = 0x00;        CSL_BootCfgSetDDRConfig(15,  ddr3config);
    ddr3config = 0x00;        CSL_BootCfgSetDDRConfig(16,  ddr3config);
    ddr3config = 0x00;        CSL_BootCfgSetDDRConfig(17,  ddr3config);
    ddr3config = 0x000000B7;  CSL_BootCfgSetDDRConfig(18,  ddr3config);
    ddr3config = 0x000000B1;  CSL_BootCfgSetDDRConfig(19,  ddr3config);
    ddr3config = 0x000000A4;  CSL_BootCfgSetDDRConfig(20,  ddr3config);
    ddr3config = 0x000000A4;  CSL_BootCfgSetDDRConfig(21,  ddr3config);
    ddr3config = 0x00000098;  CSL_BootCfgSetDDRConfig(22,  ddr3config);

    /*Do a PHY reset. Toggle DDR_PHY_CTRL_1 bit 15 0->1->0 */
    CSL_EMIF4F_GetPhyControl(&ddrPhyCtrl, &ddrPHYReadLatency);
    ddrPhyCtrl &= ~(0x00008000);
    CSL_EMIF4F_SetPhyControl(ddrPhyCtrl,  ddrPHYReadLatency);

    CSL_EMIF4F_GetPhyControl(&ddrPhyCtrl, &ddrPHYReadLatency);
    ddrPhyCtrl |= (0x00008000);
    CSL_EMIF4F_SetPhyControl(ddrPhyCtrl,  ddrPHYReadLatency);

    CSL_EMIF4F_GetPhyControl(&ddrPhyCtrl, &ddrPHYReadLatency);
    ddrPhyCtrl &= ~(0x00008000);
    CSL_EMIF4F_SetPhyControl(ddrPhyCtrl,  ddrPHYReadLatency);

    /***************** 3.4 Basic Controller and DRAM configuration ************/
    /* enable configuration */
    /*    hEmif->SDRAM_REF_CTRL    = 0x00006180; */
    CSL_EMIF4F_EnableInitRefresh();
    CSL_EMIF4F_SetRefreshRate(0x515C);

    sdram_tim1.t_wtr    = 4;
    sdram_tim1.t_rrd    = 1;
    sdram_tim1.t_rc     = 0x20;
    sdram_tim1.t_ras    = 0x17;
    sdram_tim1.t_wr     = 0x09;
    sdram_tim1.t_rcd    = 0x09;
    sdram_tim1.t_rp     = 0x09;
    CSL_EMIF4F_SetTiming1Config(&sdram_tim1);

    /*    hEmif->SDRAM_TIM_2   = 0x40877FEC; */
    sdram_tim2.t_cke    = 3;
    sdram_tim2.t_rtp    = 4;
    sdram_tim2.t_xsrd   = 0x1FF;
    sdram_tim2.t_xsnr   = 0x071;
    sdram_tim2.t_xp     = 3;
    sdram_tim2.t_odt    = 0;
    CSL_EMIF4F_SetTiming2Config (&sdram_tim2);

    /*    hEmif->SDRAM_TIM_3   = 0x55BF87FF; */
    sdram_tim3.t_rasMax     = 0xF;
    sdram_tim3.t_rfc        = 0x06A;
    sdram_tim3.t_tdqsckmax  = 0;
    sdram_tim3.zq_zqcs      = 0x3F;
    sdram_tim3.t_ckesr      = 4;
    sdram_tim3.t_csta       = 0x5;
    sdram_tim3.t_pdll_ul    = 0x5;
    CSL_EMIF4F_SetTiming3Config (&sdram_tim3);

    /*    hEmif->DDR_PHY_CTRL_1   = 0x0010010F; */
    ddrPHYReadLatency   = 0x0F;
    ddrPhyCtrl          = (0x0010010F);
    CSL_EMIF4F_SetPhyControl(ddrPhyCtrl,  ddrPHYReadLatency);

    /*    hEmif->ZQ_CONFIG        = 0x70074C1F; */
    zqcfg.zqRefInterval     = 0x4C1F;
    zqcfg.zqZQCLMult        = 3;
    zqcfg.zqZQCLInterval    = 1;
    zqcfg.zqSFEXITEn        = 1;
    zqcfg.zqDualCSEn        = 1;
    zqcfg.zqCS0En           = 1;
    zqcfg.zqCS1En           = 0;
    CSL_EMIF4F_SetOutputImpedanceConfig(&zqcfg);

    /*    hEmif->PWR_MGMT_CTRL    = 0x0; */
    pwrmgmtcfg.csTime           = 0;
    pwrmgmtcfg.srTime           = 0;
    pwrmgmtcfg.lpMode           = 0;
    pwrmgmtcfg.dpdEnable        = 0;
    pwrmgmtcfg.pdTime           = 0;
    CSL_EMIF4F_SetPowerMgmtConfig  (&pwrmgmtcfg);

    /* New value with DYN_ODT disabled and SDRAM_DRIVE = RZQ/7 */
    /*    hEmif->SDRAM_CONFIG     = 0x63077AB3; */
    CSL_EMIF4F_GetSDRAMConfig (&sdramcfg);
#if defined CHIP_6657
    sdramcfg.pageSize           = 2;
#	elif defined CHIP_6654
    //NOTE:check this again
    sdramcfg.pageSize           = 2;
#	else
	#error MKSTR(__FILE__)  MKSTR(__LINE__)
#	endif
    sdramcfg.eBank              = 0;
    sdramcfg.iBank              = 3;
    sdramcfg.rowSize            = 5;
    sdramcfg.CASLatency         = 14;
    sdramcfg.narrowMode         = 1;
#	if defined CHIP_6657
    sdramcfg.CASWriteLat        = 0;
#	elif defined CHIP_6654
    sdramcfg.CASWriteLat        = 3;
#	else
	#error MKSTR(__FILE__)  MKSTR(__LINE__)
#	endif
    sdramcfg.SDRAMDrive         = 1;
    sdramcfg.disableDLL         = 0;
    sdramcfg.dynODT             = 2;
    sdramcfg.ddrDDQS            = 0;
    sdramcfg.ddrTerm            = 2;
    sdramcfg.iBankPos           = 0;
    sdramcfg.type               = 3;
    CSL_EMIF4F_SetSDRAMConfig (&sdramcfg);

    cycles_delay(840336); /*Wait 600us for HW init to complete*/

    /* Refresh rate = (7.8*666MHz] */
    /*    hEmif->SDRAM_REF_CTRL   = 0x00001450;     */
    CSL_EMIF4F_SetRefreshRate(0x0000144F);

    /***************** 4.2.1 Partial automatic leveling ************/
    /*    hEmif->RDWR_LVL_RMP_CTRL      =  0x80000000; */
    CSL_EMIF4F_SetLevelingRampControlInfo(1, 0, 0, 0, 0);

    /* Trigger full leveling - This ignores read DQS leveling result and uses ratio forced value */
    /*    hEmif->RDWR_LVL_CTRL          =  0x80000000; */
    CSL_EMIF4F_SetLevelingControlInfo(1, 0, 0, 0, 0);

    /************************************************************
      Wait for min 1048576 DDR clock cycles for leveling to complete
      = 1048576 * 1.5ns = 1572864ns = 1.57ms.
      Actual time = ~10-15 ms
     **************************************************************/
    cycles_delay(4201680); //Wait 3ms for leveling to complete

    return (status);

}
/********************************************************************************************
 * 					Platform Specific Declarations											*
 *******************************************************************************************/

#define PLATFORM_INFO_CPU_NAME 		"TMS320C6657"
#define PLATFORM_INFO_BOARD_NAME 	"TMDXEVM6657L"

#define MEGM_REV_ID_REGISTER   (0x01812000)
#define MEGM_REV_ID_MAJ_MASK   (0xFFFF0000)
#define MEGM_REV_ID_MAJ_SHIFT  (16)
#define MEGM_REV_ID_MIN_MASK   (0x0000FFFF)
#define MEGM_REV_ID_MIN_SHIFT  (0)

#define CSL_MDIO_0_REGS                 (CSL_EMAC_SS_CFG_REGS + 0x0800)

/* Clock rate */
#	if defined CHIP_6657
	#define PLATFORM_BASE_CLK_RATE_MHZ (67)
#	elif defined CHIP_6654
	#define PLATFORM_BASE_CLK_RATE_MHZ (67)
#	else
	#error MKSTR(__FILE__)  MKSTR(__LINE__)
#endif

/* PREDIV */
#define PLATFORM_PLL_PREDIV_val (1)

/* POSTDIV */
#define PLATFORM_PLL_POSTDIV_val (2)


/* Default PLL PLLM value (100 * 20/(1*2)) = 1.0GHz) */
#	if defined CHIP_6657
//FIXME: set the correct values
	#define  PLATFORM_PLL1_PLLM_val (20)
/* Default PLL PLLD value for 1.0GHz) */
	#define  PLATFORM_PLL1_PLLD_val (1)
#	elif defined CHIP_6654
	#define  PLATFORM_PLL1_PLLM_val (25)
/* Default PLL PLLD value for 850GHz) */
	#define  PLATFORM_PLL1_PLLD_val (1)
#	else
	#error MKSTR(__FILE__)  MKSTR(__LINE__)
#endif
/* Default UART baudrate value */
#define  PLATFORM_UART_BAUDRATE_val (19200)

/* Input crystal frequency 100 MHz */
#define PLATFORM_UART_INPUT_CLOCK_RATE ((PLATFORM_BASE_CLK_RATE_MHZ * PLATFORM_PLL1_PLLM_val * 1000000)/(PLATFORM_PLL_PREDIV_val * 12 * PLATFORM_PLL1_PLLD_val)) /* SYSCLK7 = CPU_CLK/7 in Hz */

/* 1/x-rate clock for CorePac (emulation) and the ADTF module */
#define  PLATFORM_PLLDIV2_val  (3)
/* 1/y-rate clock for system trace module only */
#define  PLATFORM_PLLDIV5_val (5)
/* 1/z-rate clock is used as slow_sysclck in the system */
#define  PLATFORM_PLLDIV8_val (64)


/* LED Definitions */
#define PLATFORM_FPGA_LED_COUNT  (4)
#define PLATFORM_I2C_LED_COUNT   (0)
#define PLATFORM_TOTAL_LED_COUNT (PLATFORM_FPGA_LED_COUNT + PLATFORM_I2C_LED_COUNT)

/* Number of cores on the platform */
#define PLATFORM_CORE_COUNT 2

/* Mmeory Sections */
#define PLATFORM_L1P_BASE_ADDRESS 0x10E00000
#define PLATFORM_L1P_SIZE         0x8000    /* 32K bytes */
#define PLATFORM_L1D_BASE_ADDRESS 0x10F00000
#define PLATFORM_L1D_SIZE         0x8000    /* 32K bytes */
#define PLATFORM_DDR3_SDRAM_START 0x80000000
#define PLATFORM_DDR3_SDRAM_END   0x9FFFFFFF /* 512 MB */

/* 24AA1025 EEPROM */
#define PLATFORM_EEPROM_MANUFACTURER_ID (0x01)
#define PLATFORM_EEPROM_DEVICE_ID_1     (0x50)
#define PLATFORM_EEPROM_DEVICE_ID_2     (0x51)

/********************************************************************************************
 * 					General Declarations													*
 *******************************************************************************************/



/********************************************************************************************
 * 					Function Prototypes														*
 *******************************************************************************************/
#if (PLATFORM_SEMLOCK_IN)
#define PLIBSPILOCK() Osal_platformSpiCsEnter();
#define PLIBSPIRELEASE() Osal_platformSpiCsExit ();
#else
#define PLIBSPILOCK()
#define PLIBSPIRELEASE()
#endif

/* Function prototypes that don't live anywhere else */
//extern void configSerdes();
//extern void Init_SGMII(uint32_t macport);
extern void PowerUpDomains (void);
extern void xmc_setup();

/********************************************************************************************
 *                     PLL control local Declarations                                          *
 *******************************************************************************************/

/**
 *  Handle to access BOOTCFG registers.
 */
#define hPscCfg     ((CSL_PscRegs*)CSL_PSC_REGS)
#define hPllcRegs 	((CSL_PllcRegs*)CSL_PLL_CONTROLLER_REGS)

#define BWADJ_BIT_SHIFT     	24
#define BYPASS_BIT_SHIFT    	23
#define CLKF_BIT_SHIFT      	6

#define ENSAT_BIT_SHIFT 		6
#define RESET_BIT_SHIFT 		14

/* DDR3 PLL settings for 1333 MHz */
//NOTE:
//CLK = CLKIN × (PLLM+1) ÷ (OUTPUT_DIVIDE × (PLLD+1))

#	if defined CHIP_6657
	#define PLLM_DDR3 39
	#define PLLD_DDR3 2
#	elif defined CHIP_6654
	#define PLLM_DDR3 59
	#define PLLD_DDR3 2
#	else
	#error MKSTR(__FILE__)  MKSTR(__LINE__)
#	endif

Thank you in advance 

George

  • 0
    TI__Guru* 81335 points

    Hi George,

    It is the same bit for all the address, the 16bit in the sequence.

    For instance instead of   0xFFFF_FFFF we have 0xFFFD_FFFF. The program is halted and no interrupts runs in the system  at the time that the values changes.

    We have already run a program that test the DDR3 and no error has occurred when read/write from and to DDR3.

    Please ensure that the DDR3 (external memory) is working without any issue. You can also test that using the platform_test application provided in PDK C6657. Please find the path below.

    PATH: \ti\pdk_C6657_1_1_2_6\packages\ti\platform\evmc6657l\platform_test

    Have you selected the same part number of DDR used in EVM design or differente?

    Please follow the DDR3 initialization document and spreadsheet for the selected DDR part.

    DDR3 Design Requirements:

    Thank you.

  • 0 in reply to Raja
    Expert 1840 points

    Hello,

    We have already done the steps you described. We have test the memory using  our software test and the test that is provided by Texas instrument. 

    I was wrong before . It is not always  the 16th bit in the sequence. But it is the same bit in all the addresses that cahnges

    Thank you 

    George

  • 0 in reply to giorgos tsoumplekas
    TI__Mastermind 46460 points

    George,

    DDR3 PCB layouts must be carefully created to obtain robust operation.  The DDR3 Design Requirements for KeyStone Devices Application Report (SPRABI1B) contains guidance for creating a proper layout.  Most importantly are the guidelines for length matching and proper fly-by net routing.  Please provide a report or table showing these rules have been met.

    You provided in your post the following statement:
    NOTE: code that we use for the DDR3 initialization, provided by TI without any change
    This is not valid.  The initialization code must be adjusted to reflect the delays for each board to allow leveling to robustly converge.  We provide the KeyStone I DDR3 Initialization Application Report (SPRABL2D) which contains a detailed discussion of the initialization sequence and required adjustments.  It also come with 2 spreadsheets that must be updated for your design.  The PHY_CALC spreadsheet prompts for the information needed to calculated the leveling seed values.  The REG_CALC spreadsheet prompts for timing values from the SDRAM datasheet and for topology to properly configure the PHY and Controller registers.  Please also post these completed spreadsheets.

    Tom

  • 0 in reply to Tom Johnson 16214
    Expert 1840 points
    Hello Tom.
    I did not write that I did not do any change. I adjusted the multipliers and divider values and the PLL settings to be compatible with the board that I have. About leveling I have kept the settings that I found in the Texas. Is the levelling affected by the DDR3 ref clock ?
    THE 6657 EVM board has a ref clock at 50 Mhz but our clock has a ref clock at 66,67.


    Thank you,

    George
  • 0 in reply to giorgos tsoumplekas
    TI__Mastermind 46460 points
    George,
    It is not affected by the reference clock rate. The leveling values must be customized for each layout. Also, the controller values must be changed to match the SDRAM.
    Tom
  • 0 in reply to Tom Johnson 16214
    Expert 1840 points

    Hello Tom
    The excel documents are very helpful. About the DDR3 PHY , this document is referred in the leveling right?
    The DDR3 chip that we have is a MT41J128M16 – 16 Meg x 16 x 8 Banks.
    I try to find the length of the following requirements DQS4, CLK_4 , etc but these information are not provided in the datasheet document. Could you please give me a hint where I can find these information?

    Thank you in advance

  • 0 in reply to giorgos tsoumplekas
    TI__Mastermind 46460 points

    EVM_DDR3_Rules.xlsGiorgos,

    The routed lengths come from your PCB layout.  The layout team needed to route the board while observing the layout requirements.  Part of that is the length skew matching of the data group nets and the fly-by address, command, control and clock group nets.  They must provide a report showing the lengths and that the rules have been met.  An example is attached.

    Tom