Other Parts Discussed in Thread: AM5728
I'm porting an existing design (from TI 6482) to the new AM5728 Sitara processor. The original design uses EMIF to communicate with an FPGA, mostly for control and status. The FPGA expects a continuous EMIF clock and uses this to run a state machine and other logic to interface with the DSP. The TRM document for the AM5728 says that the GPMC clock is stopped when a synchronous access is complete, but I have read on some other forum posts of possible ways to get a continuous clock that will work for the FPGA. For example, https://e2e.ti.com/support/omap/f/885/t/374500. None of these were specifically talking about the AM5728, however.
My local TI rep suggested that clearing the AUTOIDLE bit may be able to make this clock free running. Would this work? If not, is there any other way to do this? The goal is to keep the FPGA logic intact as much as possible.
Thanks,
Jeff
