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Does KeyStone II support TwinDie DDR3?

Other Parts Discussed in Thread: 66AK2E05

Hi Champs,

Could you please let me know if KeyStone II support TwinDie x16 DDR3/DDR3L or not?

According to DDR3 Design Requirements for KeyStone Devices(SPRABI1B), KeyStone I/II don't support the DDR3.

  - Page 18

    3.1.3 x16 SDRAM

      ・ The twin-die version of the x16 SDRAM are not compatible with the monolithic
        version of the same density.

But according to KeyStone I DDR3 Initialization(SPRABL2D), KeyStone I seems to support the DDR3.

  - Page 16

    4 Dual Rank Support

      ...The procedure described in the previous sections will support DDR3 memory
      topologies using twin-die devices with the changes listed below.


So, how about KeyStone II?
There is no description about "twin-die" in Keystone II DDR3 Initialization(SPRABX7).
"twin-die" is the same meaning as "Dual Rank"?

Thank you in advance for your cooperation.

Best regards,
j-breeze

  • j-breeze,

    The terms twin-die and dual-rank are not equivalent.  Twin-die can be in same rank but recently commoditized twin-die devices are in separate ranks.

    KeyStone I devices can support up to 2 ranks but they do not support address mirroring.  Therefore, this allows twin-die devices using 2 ranks.  They do not support dual-rank DIMMs or SO-DIMMs that require address mirroring support.

    KeyStone II devices do not have any of these limitations.  They support up to 2 ranks and they can support address mirroring.  The 2 ranks can be in separate SDRAM packages or in twin-die packages.  Please note that there is also the Keystone II DDR3 Initialization Application Report (SPRABX7).

    Tom

  • Hi Tom,

    Thank you for your prompt reply.

    So, if you have any information about board designs that support KeyStone2 with Twin-Die DDR3, please let me know.

    Any comment would be appreciated.

    Best regards,
    j-breeze
  • j-breeze,

    I know of multiple customer designs but I cannot provide details.  We also implemented a layout for twin-die devices on a 66AK2E05 test board that is fully functional.  There are no special requirements for twin-die topologies.  You still need to follow the routing rules in the guidelines document.  You will discover that the additional fly-by nets for the second set of control nets will cause the fly-by routing to take more area and perhaps another layer.  I recommend that you reference the JEDEC Unbuffered DIMM Design Specification, JEDEC Standard No. 21C 4.20.19.  It provides lots of guidance for complex and dense SDRAM topologies.

    Tom

  • Hi Tom,

    Thank you for your information and advice. I'm relieved to hear that there are multipul customer designs and you have the fully functional test board.

    One of my customers is planning to use KeyStone II Device with the TwinDie DDR3L. I'll inform him of the JEDEC Specification.

    I appreciate your kind support.

    Best regards,
    j-breeze