AM335x SD card write protect pin

Hello Kazu,

Let's start with MMC driver features in AM335x Linux Processor SDK: 

The driver supports the following features:

MMC/SD native protocol command/response set
Single/multiple block data transfers
Linux file system and generic MMC layer abstract details of block devices (MMC)
High-speed (SDv1.1) and High Capacity (SDv2.0) cards
Support for 4 bit modes
Support for card detect and Write protect features
DMA and polled mode for data transfer operations

B12 pin on AM335x EVM is configured as MCASP0_ACLKR.

B12 pin is also connected to MMC_WP. To function this pin MMC0_SDWP you must select mode 4 in the corresponding Pad Control Register. 

Yes, also can configure this pin as GPIO. This pin is muxed with gpio3_18. To configure B12 as GPIO you must select mode 7 in the corresponding pad register.

Have in mind that if you configure this pin as GPIO, there is possibility to affect McASP or MMC interfaces.

Best regards,

Yanko

Hello Yanko,

Thank you for you kind reply. The schematic of our target board is being drawn now. MMC0 is used for boot function. But B12 pin is configured MCASP0_ACLKR for audio device. I can't use B12 pin which is configure MMC0_SDWP. So I'd like to use GPIO pin as function for write protect. I saw the source code of u-boot below. It looks B12 pin is configured MMC0_SDWP (not GPIO). Could I use a certain GPIO as write protect of MMC0?

u-boot/board/ti/am335x/mux.c

static struct module_pin_mux mmc0_pin_mux[] = {
 {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
 {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
 {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
 {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
 {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
 {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
 {OFFSET(mcasp0_aclkr), (MODE(4) | RXACTIVE)},  /* MMC0_WP */
 {OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */
 {-1},
};

Regards,
Kazu

Hello Kazu,

Please see the listed options about mmc0_sdwp pin:

If you will use B12 pin as GPIO you must config it in mode 7 and use gpio3_18.

However, you have two another options for mmc0_sdwp pin. This signal is muxed on pins: M18 and C18.

To configure M18 as mmc0_sdwp you must use muxmode 4.

To configure C18 as mmc0_sdwp you must use muxmode 5.

It would be better if you provide your schematic. 

Best regards,

Yanko

Hello Yanko,

Thank you for your offer, but I can't use these pins. C18 is configured as uart3_txd. M18 is configured as mdio_clk. So I can't configure write protect function using mmc0_sdwp. I want to use GPIO alternative to mmc0_sdwp. I'd like to know that Linux driver works correctly if I use GPIO for write protect.

Regards,
Kazu

Hello Kazu,

Yes, you might use any available GPIO pins for write protect functionality.

Please take a look on the threads:

Gururaja Hebbar:

Linux uses aggressive Power management method to save Power. When MMC is not in use, clock is switched off to MMC module. Because of this, if CD & WP from MMC Controller is used, Card insertion/removal or Write-protect detection will not work properly. Hence GPIO for MMC CD & WP is used.

Best regards,

Yanko

Hello Yanko,

Thank you for your reply. I think Yordan pointed out three changes in device tree.

Should I change these points?

linux-3.14.43/arch/arm/boot/dts/am335x-evm.dts

 mmc1_pins_default: pinmux_mmc1_pins {
  pinctrl-single,pins = <
   0x0F0 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mmc0_dat3.mmc0_dat3 */
   0x0F4 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mmc0_dat2.mmc0_dat2 */
   0x0F8 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mmc0_dat1.mmc0_dat1 */
   0x0FC (PIN_INPUT_PULLUP | MUX_MODE0)    /* mmc0_dat0.mmc0_dat0 */
   0x100 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mmc0_clk.mmc0_clk */
   0x104 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mmc0_cmd.mmc0_cmd */
   0x1A0 (PIN_INPUT_PULLUP | MUX_MODE7)    /* mcasp0_aclkr.gpio3_18 */
   0x160 (PIN_INPUT | MUX_MODE7)           /* spi0_cs1.gpio0_6 */
  >;
 };

&mmc1 {
 status = "okay";
 vmmc-supply = <&vmmc_reg>;
 bus-width = <4>;
 pinctrl-names = "default", "sleep";
 pinctrl-0 = <&mmc1_pins_default>;
 pinctrl-1 = <&mmc1_pins_sleep>;
 cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
 wp-gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>;
};

I'm not sure about the following change by Yordan. What should I do?

>Note that they should also configure
> &gpio3 {
> ti,no-reset-on-init;
> };

I can't find dts file for am335x gpevm in u-boot. Do I also need to change the following program?

u-boot-2014.07/board/ti/am335x/mux.c

static struct module_pin_mux mmc0_pin_mux[] = {
 {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
 {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
 {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
 {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
 {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
 {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
 {OFFSET(mcasp0_aclkr), (MODE(4) | RXACTIVE)},  /* MMC0_WP */
 {OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */
 {-1},
};

Regards,
Kazu

Hello Yanko,

I appreciate your help. I'm sorry for not explaining clearly. And I can't send our schematic. The am335x-evm.dts and mux.c in my previous post are default program of gp evm in Processor SDK. I can understand that write protect functionality is used B12 pin as mmc0_wp in u-boot and is used B12 pin as gpio3_18 in kernel. I have to change the pin from B12 to a certain undecided pin. I can understand modifications now.

Regards,
Kazu