GPMC_CLK Gating

Jason Williams61

Is there a way to configure the DM8168 to leave the output (synchronous mode) GPMC_CLK on continuously? Internal FPGA synchronization would be easier if the clock was on all the time.

Thanks,
Jason

over 10 years ago

0 Pavel Botev over 10 years ago

TI__Guru**** 170625 points

Hi Jason,

It is not possible to have it running all the time. The GPMC_CLK clock is only activated when the access in progress is defined as synchronous (read or write access). The GPMC_CLK clock is stopped when cycle time completes and is asserted low between accesses.

See also the below pointers:

e2e.ti.com/.../766086
e2e.ti.com/.../119840

BR
Pavel

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GPMC_CLK Gating