We are reviewing customer's TPS65910 PMIC power sequencing on AM3352. I noticed that in the reference design the PMIC BOOT mode is 01 (BOOT 1 pin strapped to VRTC). Looking at the boot mode timing characteristics I notice that it begins when PWRHOLD transitions high. But the reference designs have the power hold pin interfacing the PMIC_POWER_EN pin on the AM3352. I’m wondering how this actually works seeing as the AM3352 isn’t powered up yet. Figuring I’m missing something easy, but I didn’t really find a good description in the tech ref manual …. Well not that I could find anyway.
Also we are looking to use a CPLD to initiate the startup via the PWRON pin (it actually sequences power on of all systems on the board) … is there any conflict with the PWRHOLD pin in doing this?
Thanks,
Mark
