Hi,
A compliance test of DDR3 of AM437x fails in the following items.
tCK(avg) Rising Edge Measurements
fail :2.496 ns -0.5 % 2.500 ns <= VALUE <= 3.300 ns
Try the following:
1. Change impedance and a through rate of CK/CK# in Table 7-287.CTRL_DDR_ADDRCTRL_IOCTRL registers of TRM.
2. Exclude terminal resistance of CK/CK# and raise the reflection of the pattern on purpose.
refclk is 24MHz.
set register of the DPLL DDR is as follows:
6.13.8.36 PRCM_CM_CLKSEL_DPLL_DDR Register (Offset = 5ACh) :0x00003202
6.13.8.37 PRCM_CM_DIV_M2_DPLL_DDR Register (Offset = 5B0h) :0x00000221
6.13.8.38 PRCM_CM_DIV_M4_DPLL_DDR Register (Offset = 5B8h) :0x00000222
What kind of thing is necessary so that tck(avg) becomes by all means than 2.5ns?
Best Regards,
Shigehiro Tsuda
