Dear all,
I am trying to configure the DDR3 PLL for a C6654 platform . The DDR3 chip is the following MT41J128M16 – 16 Meg x 16 x 8 Banks. I have gone through the document spreadsheets that are provided by TI.
I am using the configuration for the evmc6657 as a reference.
But I have a question regarding the implementation that is provided by TI in evmc6657.c file.
Regarding the document sprugv2f.pdf, section 3.5 in the step 6 , says " Wait for at least 5 μs based on the reference clock (PLL reset time):. In the implementation in the corresponding piece of code the delay is
/*Wait for PLL to lock min 5 micro seconds*/
pll_delay(7000);
Which is the frequency that is used for calculate the number of the cycles that are passed as argument.
For my implementation the input clock is 66,67 Mhz and the output clock for the processor is 850 Mhz and for the DDR3 is 667 and I try to understand if these delays are fit in my implementation.
Best regards
George
