AM335x UART Pulse duration requirement

Hi,

Please check section 4.4.4.2.1 from the AM335X TRM Rev. L. It says:

"When the UART is receiving, the bit is sampled in the 8th BCLK cycle for 16× over sampling mode and on the 6th BCLK cycle for 13× oversampling mode."

Therefore oversampling does not mean the bit timing should be looser. Furthermore if the receiver character has all bits distorted in the same direction this would mean a total distortion of 4%*9=36%, respectively 5%*9=45% for the whole character (start bit + 8 data bits), and this is quite a loose tolerance.

Daisuke Maeda said:

The description that you showed explains UART in PRU. Can it be applied to general UART?

Yes, UARTs are the same.

Daisuke Maeda said:

Is the pulse duration requirement (0.96U-1.05U) the tolerance to correctly receive the whole character (start bit + 8 data bits)? When parity bit and stop bits are used, is it same?

Yes, this tolerance is the same for each bit received. By the way my previous calculations are not correct. The same tolerance applies for the whole character (start + data + parity + stop bits) - allowed distortion is from -4% to +5%.