Other Parts Discussed in Thread: AM3352
Hello,
we have a phycore module with AM3352 processor and NAND flash 1GB. (http://phytec.com/products/system-on-modules/phycore/am335x/)
We have own baseboard for these module. It's generally works fine but sometimes we have problem with MLO which is located on NAND memory.
The error sfrom Barebox MLO are like this:
barebox 2013.07.0-PD13.1.0 MLO PCM-051-23102F0I.A0_V1 #1 Wed Sep 18 13:48:56 CEST 2013
Board: Phytec phyCORE-AM335x
omap-hsmmc omap4-hsmmc0: registered as omap4-hsmmc0
mci0: registered disk0
m25p80 m25p800: unrecognized JEDEC id ffffff
m25p80 m25p800: probe failed: error 19
probe buswidth
nand: ONFI param page 0 valid
nand: ONFI flash detected ...
nand: Manufacturer ID: 0x2c, Chip ID: 0xd3 (Micron MT29F8G08ADADAH4), page size: 2048, OOB size: 64
booting from NAND
unable to handle paging request at address 0x422ffa13
pc : [<402f9192>] lr : [<402f4b87>]
sp : 87ffff78 ip : 00000016 fp : 00029940
r10: 00029940 r9 : 402f0409 r8 : 4030cdcc
r7 : 08000000 r6 : 86ffdc88 r5 : 422ffa13 r4 : 402fd28f
r3 : 00000000 r2 : 00000000 r1 : 422ffa13 r0 : 86ffdc88
Flags: nZCv IRQs off FIQs on Mode SVC_32
no stack data available
or
barebox 2013.07.0-PD13.1.0 MLO PCM-051-23102F0I.A0_V1 #1 Wed Sep 18 13:48:56 CEST 2013
Board: Phytec phyCORE-AM335x
undefined instruction
pc : [<402fcef4>] lr : [<402fcef3>]
sp : 87ffffa8 ip : 00000800 fp : 00100000
r10: 86ffe000 r9 : 4030299c r8 : 00000c00
r7 : 00400000 r6 : 4030299c r5 : 870fdc01 r4 : 86ffa820
r3 : 0000003f r2 : 00000040 r1 : 87ffc000 r0 : 87ffc000
Flags: nZCv IRQs off FIQs on Mode SVC_32
no stack data available
I also checked the trace vectors and output is this:
CONTROL: device_id = 0x2b94402e
* AM335x family
* Silicon Revision 2.1
PRM_DEVICE: PRM_RSTST = 0x00000003
* Bit 0 : GLOBAL_COLD_RST
* Bit 1 : GLOBAL_WARM_RST
CONTROL: control_status = 0x00820333
* SYSBOOT[15:14] = 10b (25 MHz)
* SYSBOOT[11:10] = 00b No GPMC CS0 addr/data muxing
* SYSBOOT[9] = 0 GPMC CS0 Ignore WAIT input
* SYSBOOT[9] = 1 GPMC CS0 Use WAIT input
* Device Type = General Purpose (GP)
* SYSBOOT[7:6] = 00b MII (EMAC boot modes only)
* SYSBOOT[5] = 1 CLKOUT1 enabled
* Boot Sequence : NAND -> NANDI2C -> MMC0 -> UART0
ROM: Current tracing vector, word 1 = 0x0010009e
* Bit 1 : [General] Entered main function
* Bit 2 : [General] Running after the cold reset
* Bit 3 : [Boot] Main booting routine entered
* Bit 4 : [Memory Boot] Memory booting started
* Bit 7 : [Boot] GP header found
* Bit 20 : [Configuration Header] CHSETTINGS found
ROM: Current tracing vector, word 1 = 0x00018000
* Bit 15 : [Memory Boot] Memory booting trial 3
* Bit 16 : [Memory Boot] Execute GP image
ROM: Current tracing vector, word 1 = 0x00000020
* Bit 5 : [Memory Boot] Memory booting device MMCSD0
ROM: Current copy of PRM_RSTST = 0x00000000
ROM: Cold reset tracing vector, word 1 = 0x00000000
ROM: Cold reset tracing vector, word 1 = 0x00000000
ROM: Cold reset tracing vector, word 1 = 0x00000003
* Bit 0 : [Memory Boot] Memory booting device NULL
* Bit 1 : [Memory Boot] Memory booting device XIP
Cortex A8 Program Counter = 0x00025568
ROM Exception Vectors
* 0x4030CE04 Undefined
* 0x4030CE08 SWI
* 0x4030CE0C Pre-fetch abort
* 0x4030CE10 Data abort
* 0x4030CE14 Unused
* 0x4030CE18 IRQ
* 0x4030CE1C FIQ
ROM Dead Loops
* 0x00020080 Undefined exception default handler
* 0x00020084 SWI exception default handler
* 0x00020088 Pre-fetch abort exception default handler
* 0x0002008C Data exception default handler
* 0x00020090 Unused exception default handler
* 0x00020094 IRQ exception default handler
* 0x00020098 FIQ exception default handler
* 0x0002009C Validation test PASS
* 0x000200A0 Validation test FAIL
* 0x000200A4 Reserved
* 0x000200A8 Image not executed or returned
* 0x000200AC Reserved
* 0x000200B0 Reserved
* 0x000200B4 Reserved
* 0x000200B8 Reserved
* 0x000200BC Reserved
Can you have any idea where is problem, is it problem with NAND ? If the MLO is reflashed then the box is running OK.
Is it there any way how to solve this problem ?
Thanks.
Tomas Krcka
