Jacinto 5 Eco SPI problems, only data in Rx if I send to many words and XFERLEVEL does not change after the second write.

Hi Staffan,

Are you using J5Eco TI EVM or custom board?

Note that on J5Eco TI EVM, there is SPI flash (W25X32V3FIG) attached to SPI0 (D1 is MOSI, DO is MISO). I would recommend you to check and align to the SPI flash CCS test, available to download at:

support.spectrumdigital.com/.../reve -> Test Code

j5ecoevm/tests/spiflash/

BR
Pavel

I use SPI1 and there is an EEPROM as slave and I get an answer so I do not need another test, I need to figure out why my current test is not working.

1. Send WREN - works, I can see it being sent on the oscilloscope.

2. Send dummy command to get answer from EEPROM - works, I can see the answer on the oscilloscope!

3. Read from Rx - FAILS, there is no data there unless I send another 2 dummy words. 

How can this be? This seems to be some issue with the FIFO.

Staffan,

Staffan Johansson said:

I need to figure out why my current test is not working

Can you provide me the steps to reproduce this issue on the J5Eco EVM?

Staffan Johansson said:

1. Send WREN - works, I can see it being sent on the oscilloscope.

Can you provide more details regarding WREN? I can not find such bit or signal in the J5Eco TRM McSPI chapter.

Staffan Johansson said:

3. Read from Rx - FAILS, there is no data there unless I send another 2 dummy words. 

How can this be? This seems to be some issue with the FIFO.

Make sure only one channel is selected to use the FIFO. If you disable the FIFO, will you get the data you expect in RX register? Check If your FIFO is configured for 3 words to hold before transfer to RX register. Monitor the MCSPI_IRQSTATUS register. Provide McSPI register dump just before to start/initiate the data transfer.

BR
Pavel

Thnx for the reply.

WREN is a command to the EEPROM, write enable. Means I sen 0x06 on the SPI bus. Is there an EEPROM on the EVM board? I use a custom board now.


"Check If your FIFO is configured for 3 words to hold before transfer to RX register."
You mean AFL/AEL? I set it to a quarter of the total FIFO size, in my case 64/4 = 16.
Exactly what do you mean by the above?
I set WCNT to 2 because I want to Tx 2 words.

I also noticed now that when I send 3 8bit words only the data for the first word is sent.

I can see the data in Tx change from 0xAA to 0xBB to 0xCC but on the oscilloscope I only see 0xAA and then 0 and 0.




Here is some code:
static void configHwChannelForTxRx(uint32 hwUnit, uint32 hwChan, uint32 wordLength, uint16 numWordsToTransmit)
{
uint32 regVal;

regVal = Spi_HwRegs[hwUnit].MCSPI_CHn[hwChan].MCSPI_CHnCONF & (~MCSPI_CHnCONF_WL_MASK);
Spi_HwRegs[hwUnit].MCSPI_CHn[hwChan].MCSPI_CHnCONF = regVal | ((wordLength - 1) << MCSPI_WL_OFFSET);

regVal = *Spi_HwRegs[hwUnit].MCSPI_XFERLEVEL & (~MCSPI_XFERLEVEL_WCNT_MASK);
#if 0
numWordsToTransmit = numWordsToTransmit == 2 ? numWordsToTransmit * 2 : numWordsToTransmit;
#elif 0
numWordsToTransmit = numWordsToTransmit == 2 ? numWordsToTransmit : numWordsToTransmit * 2;
#endif
*Spi_HwRegs[hwUnit].MCSPI_XFERLEVEL = regVal | (numWordsToTransmit << MCSPI_WCNT_OFFSET);
}

static void startHwChannelTxRx(uint32 hwUnit, uint32 hwChan, Spi_CallTypeType callType)
{
uint32 regVal;

Spi_Mcspi_ClearAllIrqStatus(hwUnit);

Spi_HwRegs[hwUnit].MCSPI_CHn[hwChan].MCSPI_CHnCONF |= MCSPI_CHnCONF_FFEW_FFER_MASK;

if ((callType == SPI_ASYNC_CALL) && (Spi_Global.asyncMode == SPI_INTERRUPT_MODE))
{
#if 0 // ok to enable for all channelss?
Spi_Hw_EnableInterrupt(hwUnit);
#else
regVal = (
(MCSPI_IRQSTATUS_TXn_EMPTY_MASK(hwChan)) |
(MCSPI_IRQSTATUS_RXn_FULL_MASK(hwChan)));
/* Rx overflow interrupt only exists for channel 0. */
if (hwChan == 0)
{
regVal |= MCSPI_IRQSTATUS_RX0_OVERFLOW_MASK;
}
*Spi_HwRegs[hwUnit].MCSPI_IRQENABLE = regVal;
#endif
}

/* Keep chip select active between SPI words. */
Spi_HwRegs[hwUnit].MCSPI_CHn[hwChan].MCSPI_CHnCONF |= (MCSPI_FORCE << MCSPI_FORCE_OFFSET);

enableMcSpiChannel(hwUnit, hwChan);
}


Then I write the data like this once for each word and I can, as I wrote above, see Txn change.:
hwPtr->MCSPI_CHn[chipSelect].MCSPI_TXn = data;

I guess I must have misunderstood how the FIFO works. Is it not enough to configure WCNT (number of words in XFERLEVEL) etc as in above posts and then put stuff in TXn (I have configured Txn to be used for the FIFO)? Do I need to check status before I put the next word in?
Seems weird that it transmits something (0) but not what I tell it to.

I see a problem now but it might be because I debug and step through the program.

After I put the first word into the FIFO I get EOT and EOW and not after I put all 3 words in. How can this be?


Unfortuneately the manual never shows how to fill the FIFO:
Configure the channel according to the mode. See Table 21-7.
Start the channel. MCSPI_CHxCTRL[0] EN 0x1
Wait until end of word count? MCSPI_IRQSTATUS[17] EOW = 0x1
Stop the channel. MCSPI_CHxCTRL[0] EN 0x0
Read from the receiver register. MCSPI_RXx xxxx

Have I misunderstood this and it should be filled before enabling the channel!? But enabling the channel resets the FIFO, am I not right?

Staffan,

In J5Eco McSPI master mode - SPI initiates a data transfer on the data lines (SPI_D[1:0]) and generates clock (SPI_SCLK) and control signals (SPI_SCS[n]) to a single SPI slave device.

We have 3 types of master modes:
1. Master Transmit and Receive Mode - section 21.2.3.3
2. Master Transmit-Only Mode - section 21.2.3.4
3. Master Receive-Only Mode - section 21.2.3.5

From what I understand, you are using master transmit and receive mode, right?


BR
Pavel

Yes, TRM.

It would be great with a small working example using FIFO, just the minimal to get it to send and receive. You don't happen to have that?